Development of Racetrack Memories

On-chip racetrack memory

Project details

It is anticipated that the basic research and material science undertaken could lead to practical application and implementation on a 4-7 year timescale. This project will enable the PI to focus on demonstrating this new memory architecture with the access to the characterisation and on-chip implementation facilities in the Hitachi Cambridge Laboratory (HCL). This will encourage the exchange between York and HCL, and will further strengthen the relationship. Therefore this project will provide a great opportunity for the PI and his group to work with a worldleading industry.

Funding agency

Royal Society (Industry Fellowship, value: GBP 65,200)

Starting date

01/10/2013 (for 4 years).

Ending date

30/09/2015 (successfully completed).