cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: logic Date: 12-14-2016, 9:00AM
Device Used: XC9572XL-5-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
5 /72 ( 7%) 5 /360 ( 1%) 9 /216 ( 4%) 0 /72 ( 0%) 14 /34 ( 41%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 0/18 0/54 0/90 5/ 9
FB2 5/18 9/54 5/90 5/ 9
FB3 0/18 0/54 0/90 2/ 9
FB4 0/18 0/54 0/90 2/ 7
----- ----- ----- -----
5/72 9/216 5/360 14/34
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 9 9 | I/O : 10 28
Output : 5 5 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 2 2
GCK : 0 0 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 14 14
** Power Data **
There are 5 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'logic.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'ctl_in_3_A' based upon the LOC
constraint 'P43'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal
'ctl_out_3_A_OBUF' is ignored. Most likely the signal is gated and therefore
cannot be used as a global control signal.
************************* Summary of Mapped Logic ************************
** 5 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
ctl_out_3_A 1 1 FB2_9 33 GSR/I/O O STD FAST
ctl_out_2_B 1 3 FB2_11 34 GTS/I/O O STD FAST
ctl_out_2_A 1 3 FB2_14 36 GTS/I/O O STD FAST
ctl_out_1_B 1 3 FB2_15 37 I/O O STD FAST
ctl_out_1_A 1 3 FB2_17 38 I/O O STD FAST
** 9 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
ctl_in_1_A FB1_2 39 I/O I
ctl_in_1_B FB1_5 40 I/O I
ctl_in_2_A FB1_6 41 I/O I
ctl_in_2_B FB1_8 42 I/O I
ctl_in_3_A FB1_9 43 GCK/I/O I
sw_1_A FB3_16 18 I/O I
sw_1_B FB3_17 16 I/O I
sw_2_B FB4_2 19 I/O I
sw_2_A FB4_5 20 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 39 I/O I
(unused) 0 0 0 5 FB1_3 (b)
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 40 I/O I
(unused) 0 0 0 5 FB1_6 41 I/O I
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 42 I/O I
(unused) 0 0 0 5 FB1_9 43 GCK/I/O I
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 44 GCK/I/O
(unused) 0 0 0 5 FB1_12 (b)
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 1 GCK/I/O
(unused) 0 0 0 5 FB1_15 2 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 3 I/O
(unused) 0 0 0 5 FB1_18 (b)
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 29 I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 30 I/O
(unused) 0 0 0 5 FB2_6 31 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 32 I/O
ctl_out_3_A 1 0 0 4 FB2_9 33 GSR/I/O O
(unused) 0 0 0 5 FB2_10 (b)
ctl_out_2_B 1 0 0 4 FB2_11 34 GTS/I/O O
(unused) 0 0 0 5 FB2_12 (b)
(unused) 0 0 0 5 FB2_13 (b)
ctl_out_2_A 1 0 0 4 FB2_14 36 GTS/I/O O
ctl_out_1_B 1 0 0 4 FB2_15 37 I/O O
(unused) 0 0 0 5 FB2_16 (b)
ctl_out_1_A 1 0 0 4 FB2_17 38 I/O O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: ctl_in_1_A 4: ctl_in_2_B 7: sw_1_B
2: ctl_in_1_B 5: ctl_in_3_A 8: sw_2_A
3: ctl_in_2_A 6: sw_1_A 9: sw_2_B
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ctl_out_3_A ....X................................... 1
ctl_out_2_B ..XX...X................................ 3
ctl_out_2_A ..XX....X............................... 3
ctl_out_1_B XX....X................................. 3
ctl_out_1_A XX...X.................................. 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 5 I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 6 I/O
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 7 I/O
(unused) 0 0 0 5 FB3_9 8 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 12 I/O
(unused) 0 0 0 5 FB3_12 (b)
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 13 I/O
(unused) 0 0 0 5 FB3_15 14 I/O
(unused) 0 0 0 5 FB3_16 18 I/O I
(unused) 0 0 0 5 FB3_17 16 I/O I
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 19 I/O I
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 20 I/O I
(unused) 0 0 0 5 FB4_6 (b)
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 21 I/O
(unused) 0 0 0 5 FB4_9 (b)
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 22 I/O
(unused) 0 0 0 5 FB4_12 (b)
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 23 I/O
(unused) 0 0 0 5 FB4_15 27 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 28 I/O
(unused) 0 0 0 5 FB4_18 (b)
******************************* Equations ********************************
********** Mapped Logic **********
ctl_out_1_A <= (ctl_in_1_A AND NOT sw_1_A AND NOT ctl_in_1_B);
ctl_out_1_B <= (NOT ctl_in_1_A AND ctl_in_1_B AND NOT sw_1_B);
ctl_out_2_A <= (ctl_in_2_A AND NOT sw_2_B AND NOT ctl_in_2_B);
ctl_out_2_B <= (NOT ctl_in_2_A AND ctl_in_2_B AND NOT sw_2_A);
ctl_out_3_A <= ctl_in_3_A;
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572XL-5-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC9572XL-5-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 23 KPR
2 KPR 24 TDO
3 KPR 25 GND
4 GND 26 VCC
5 KPR 27 KPR
6 KPR 28 KPR
7 KPR 29 KPR
8 KPR 30 KPR
9 TDI 31 KPR
10 TMS 32 KPR
11 TCK 33 ctl_out_3_A
12 KPR 34 ctl_out_2_B
13 KPR 35 VCC
14 KPR 36 ctl_out_2_A
15 VCC 37 ctl_out_1_B
16 sw_1_B 38 ctl_out_1_A
17 GND 39 ctl_in_1_A
18 sw_1_A 40 ctl_in_1_B
19 sw_2_B 41 ctl_in_2_A
20 sw_2_A 42 ctl_in_2_B
21 KPR 43 ctl_in_3_A
22 KPR 44 KPR
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-5-VQ44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25