| Design Name | logic |
| Fitting Status | Successful |
| Software Version | P.20131013 |
| Device Used | XC9572XL-5-VQ44 |
| Date | 12-14-2016, 9:00AM |
| Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
|---|---|---|---|---|
| 5/72 (7%) | 5/360 (2%) | 0/72 (0%) | 14/34 (42%) | 9/216 (5%) |
|
|
| Global clock net(s) used | 0 |
| Global output enable net(s) used | 0 |
| Global set/rest net(s) used | 0 |
| Macrocells in high performance mode (MCHP) | 5 |
| Macrocells in low power mode (MCLP) | 0 |
| Total macrocells used (MC) | 5 |