 
cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: top                                 Date:  9-30-2015,  9:38AM
Device Used: XC9572XL-5-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
37 /72  ( 51%) 175 /360  ( 49%) 62 /216 ( 29%)   25 /72  ( 35%) 18 /34  ( 53%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          14/18       21/54       81/90       8/ 9
FB2          17/18       21/54       74/90       7/ 9
FB3           6/18       20/54       20/90       3/ 9
FB4           0/18        0/54        0/90       0/ 7
             -----       -----       -----      -----    
             37/72       62/216     175/360     18/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Signal 'CLR' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    4           4    |  I/O              :    13      28
Output        :   12          12    |  GCK/IO           :     2       3
Bidirectional :    0           0    |  GTS/IO           :     2       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     18          18

** Power Data **

There are 37 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'top.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK' based upon the LOC
   constraint 'P44'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
*************************  Summary of Mapped Logic  ************************

** 12 Outputs **

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
LED3                        8     7     FB1_2   39   I/O     O       STD  FAST 
LED2                        4     7     FB1_5   40   I/O     O       STD  FAST 
LED1                        7     7     FB1_6   41   I/O     O       STD  FAST 
LED0                        6     7     FB1_8   42   I/O     O       STD  FAST 
LED4                        5     6     FB1_14  1    GCK/I/O O       STD  FAST 
LED5                        6     6     FB1_15  2    I/O     O       STD  FAST 
LED6                        5     6     FB1_17  3    I/O     O       STD  FAST 
RM1                         6     7     FB2_11  34   GTS/I/O O       STD  FAST 
RM0                         7     7     FB2_14  36   GTS/I/O O       STD  FAST 
LM1                         4     7     FB2_15  37   I/O     O       STD  FAST 
LM0                         8     7     FB2_17  38   I/O     O       STD  FAST 
LED7                        1     2     FB3_2   5    I/O     O       STD  FAST 

** 25 Buried Nodes **

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
XLXI_33/XLXI_9/Q<0>         18    8     FB1_1   STD  RESET
XLXI_46/PS1                 2     13    FB1_9   STD  RESET
XLXI_33/XLXI_9/Q<5>         4     5     FB1_10  STD  RESET
XLXI_33/XLXI_9/Q<4>         4     5     FB1_11  STD  RESET
XLXI_33/XLXI_9/Q<3>         4     5     FB1_12  STD  RESET
XLXI_33/XLXI_9/Q<2>         4     5     FB1_13  STD  RESET
XLXI_33/XLXI_9/Q<1>         4     5     FB1_16  STD  RESET
XLXI_27/XLXI_97/XLXN_282    1     1     FB2_2   STD  RESET
XLXI_27/XLXN_342            4     17    FB2_3   STD  RESET
XLXI_27/XLXN_341            4     16    FB2_4   STD  RESET
XLXI_27/XLXN_340            4     15    FB2_5   STD  RESET
XLXI_27/XLXI_96/Q0          4     14    FB2_6   STD  RESET
XLXI_27/XLXI_68/Q<7>        4     13    FB2_7   STD  RESET
XLXI_27/XLXI_68/Q<6>        4     12    FB2_8   STD  RESET
XLXI_27/XLXI_68/Q<5>        4     11    FB2_9   STD  RESET
XLXI_27/XLXI_68/Q<4>        4     10    FB2_10  STD  RESET
XLXI_27/XLXI_68/Q<3>        4     9     FB2_12  STD  RESET
XLXI_27/XLXI_68/Q<2>        4     8     FB2_13  STD  RESET
XLXI_27/XLXI_68/Q<1>        4     7     FB2_16  STD  RESET
XLXI_27/XLXI_68/Q<0>        4     6     FB2_18  STD  RESET
XLXI_27/XLXI_97/XLXN_281    1     1     FB3_14  STD  RESET
XLXI_46/PS2                 3     16    FB3_15  STD  RESET
XLXI_33/XLXI_9/XLXI_7/Q<6>  4     5     FB3_16  STD  RESET
XLXI_33/XLXI_9/Q<7>         4     5     FB3_17  STD  RESET
XLXI_46/PS0                 7     16    FB3_18  STD  RESET

** 6 Inputs **

Signal                      Loc     Pin  Pin     Pin     
Name                                No.  Type    Use     
CLK                         FB1_11  44   GCK/I/O GCK
Dark                        FB2_6   31   I/O     I
Timer_in                    FB2_8   32   I/O     I
CLR                         FB2_9   33   GSR/I/O GSR
Tilt                        FB3_8   7    I/O     I
Enable                      FB3_16  18   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
XLXI_33/XLXI_9/Q<0>  18      13<-   0   0     FB1_1         (b)     (b)
LED3                  8       8<- /\5   0     FB1_2   39    I/O     O
(unused)              0       0   /\5   0     FB1_3         (b)     (b)
(unused)              0       0   /\3   2     FB1_4         (b)     (b)
LED2                  4       0   \/1   0     FB1_5   40    I/O     O
LED1                  7       2<-   0   0     FB1_6   41    I/O     O
(unused)              0       0   /\1   4     FB1_7         (b)     (b)
LED0                  6       1<-   0   0     FB1_8   42    I/O     O
XLXI_46/PS1           2       0   /\1   2     FB1_9   43    GCK/I/O (b)
XLXI_33/XLXI_9/Q<5>   4       0     0   1     FB1_10        (b)     (b)
XLXI_33/XLXI_9/Q<4>   4       0   \/1   0     FB1_11  44    GCK/I/O GCK
XLXI_33/XLXI_9/Q<3>   4       1<- \/2   0     FB1_12        (b)     (b)
XLXI_33/XLXI_9/Q<2>   4       2<- \/3   0     FB1_13        (b)     (b)
LED4                  5       3<- \/3   0     FB1_14  1     GCK/I/O O
LED5                  6       3<- \/2   0     FB1_15  2     I/O     O
XLXI_33/XLXI_9/Q<1>   4       2<- \/3   0     FB1_16        (b)     (b)
LED6                  5       3<- \/3   0     FB1_17  3     I/O     O
(unused)              0       0   \/5   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Dark                   8: XLXI_27/XLXI_68/Q<4>  15: XLXI_33/XLXI_9/Q<3> 
  2: Enable                 9: XLXI_27/XLXI_68/Q<5>  16: XLXI_33/XLXI_9/Q<4> 
  3: Tilt                  10: XLXI_27/XLXI_68/Q<6>  17: XLXI_33/XLXI_9/Q<5> 
  4: XLXI_27/XLXI_68/Q<0>  11: XLXI_27/XLXI_68/Q<7>  18: XLXI_33/XLXI_9/Q<7> 
  5: XLXI_27/XLXI_68/Q<1>  12: XLXI_33/XLXI_9/Q<0>   19: XLXI_46/PS0 
  6: XLXI_27/XLXI_68/Q<2>  13: XLXI_33/XLXI_9/Q<1>   20: XLXI_46/PS1 
  7: XLXI_27/XLXI_68/Q<3>  14: XLXI_33/XLXI_9/Q<2>   21: XLXI_46/PS2 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_33/XLXI_9/Q<0>  ...........X..XXXXXXX................... 8
LED3                 .X.........XXX....XXX................... 7
LED2                 .X.........XXX....XXX................... 7
LED1                 .X.........XXX....XXX................... 7
LED0                 .X.........XXX....XXX................... 7
XLXI_46/PS1          X.XXXXXXXXX.......XXX................... 13
XLXI_33/XLXI_9/Q<5>  ...............XX.XXX................... 5
XLXI_33/XLXI_9/Q<4>  ..............XX..XXX................... 5
XLXI_33/XLXI_9/Q<3>  .............XX...XXX................... 5
XLXI_33/XLXI_9/Q<2>  ............XX....XXX................... 5
LED4                 ...........XXX....XXX................... 6
LED5                 ...........XXX....XXX................... 6
XLXI_33/XLXI_9/Q<1>  ...........XX.....XXX................... 5
LED6                 ...........XXX....XXX................... 6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB2_1         (b)     (b)
XLXI_27/XLXI_97/XLXN_282
                      1       0     0   4     FB2_2   29    I/O     (b)
XLXI_27/XLXN_342      4       0     0   1     FB2_3         (b)     (b)
XLXI_27/XLXN_341      4       0     0   1     FB2_4         (b)     (b)
XLXI_27/XLXN_340      4       0     0   1     FB2_5   30    I/O     (b)
XLXI_27/XLXI_96/Q0    4       0     0   1     FB2_6   31    I/O     I
XLXI_27/XLXI_68/Q<7>
                      4       0     0   1     FB2_7         (b)     (b)
XLXI_27/XLXI_68/Q<6>
                      4       0     0   1     FB2_8   32    I/O     I
XLXI_27/XLXI_68/Q<5>
                      4       0     0   1     FB2_9   33    GSR/I/O GSR
XLXI_27/XLXI_68/Q<4>
                      4       0   \/1   0     FB2_10        (b)     (b)
RM1                   6       1<-   0   0     FB2_11  34    GTS/I/O O
XLXI_27/XLXI_68/Q<3>
                      4       0     0   1     FB2_12        (b)     (b)
XLXI_27/XLXI_68/Q<2>
                      4       0   \/1   0     FB2_13        (b)     (b)
RM0                   7       2<-   0   0     FB2_14  36    GTS/I/O O
LM1                   4       0   /\1   0     FB2_15  37    I/O     O
XLXI_27/XLXI_68/Q<1>
                      4       0   \/1   0     FB2_16        (b)     (b)
LM0                   8       3<-   0   0     FB2_17  38    I/O     O
XLXI_27/XLXI_68/Q<0>
                      4       1<- /\2   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Enable                 8: XLXI_27/XLXI_68/Q<6>      15: XLXI_27/XLXN_342 
  2: XLXI_27/XLXI_68/Q<0>   9: XLXI_27/XLXI_68/Q<7>      16: XLXI_33/XLXI_9/Q<0> 
  3: XLXI_27/XLXI_68/Q<1>  10: XLXI_27/XLXI_96/Q0        17: XLXI_33/XLXI_9/Q<1> 
  4: XLXI_27/XLXI_68/Q<2>  11: XLXI_27/XLXI_97/XLXN_281  18: XLXI_33/XLXI_9/Q<2> 
  5: XLXI_27/XLXI_68/Q<3>  12: XLXI_27/XLXI_97/XLXN_282  19: XLXI_46/PS0 
  6: XLXI_27/XLXI_68/Q<4>  13: XLXI_27/XLXN_340          20: XLXI_46/PS1 
  7: XLXI_27/XLXI_68/Q<5>  14: XLXI_27/XLXN_341          21: XLXI_46/PS2 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_27/XLXI_97/XLXN_282 
                     ..........X............................. 1
XLXI_27/XLXN_342     .XXXXXXXXXXXXXX...XXX................... 17
XLXI_27/XLXN_341     .XXXXXXXXXXXXX....XXX................... 16
XLXI_27/XLXN_340     .XXXXXXXXXXXX.....XXX................... 15
XLXI_27/XLXI_96/Q0   .XXXXXXXXXXX......XXX................... 14
XLXI_27/XLXI_68/Q<7> 
                     .XXXXXXXX.XX......XXX................... 13
XLXI_27/XLXI_68/Q<6> 
                     .XXXXXXX..XX......XXX................... 12
XLXI_27/XLXI_68/Q<5> 
                     .XXXXXX...XX......XXX................... 11
XLXI_27/XLXI_68/Q<4> 
                     .XXXXX....XX......XXX................... 10
RM1                  X..............XXXXXX................... 7
XLXI_27/XLXI_68/Q<3> 
                     .XXXX.....XX......XXX................... 9
XLXI_27/XLXI_68/Q<2> 
                     .XXX......XX......XXX................... 8
RM0                  X..............XXXXXX................... 7
LM1                  X..............XXXXXX................... 7
XLXI_27/XLXI_68/Q<1> 
                     .XX.......XX......XXX................... 7
LM0                  X..............XXXXXX................... 7
XLXI_27/XLXI_68/Q<0> 
                     .X........XX......XXX................... 6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               20/34
Number of signals used by logic mapping into function block:  20
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB3_1         (b)     (b)
LED7                  1       0     0   4     FB3_2   5     I/O     O
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   6     I/O     
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   7     I/O     I
(unused)              0       0     0   5     FB3_9   8     I/O     
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  12    I/O     
(unused)              0       0     0   5     FB3_12        (b)     
(unused)              0       0     0   5     FB3_13        (b)     
XLXI_27/XLXI_97/XLXN_281
                      1       0     0   4     FB3_14  13    I/O     (b)
XLXI_46/PS2           3       0     0   2     FB3_15  14    I/O     (b)
XLXI_33/XLXI_9/XLXI_7/Q<6>
                      4       0     0   1     FB3_16  18    I/O     I
XLXI_33/XLXI_9/Q<7>   4       0   \/1   0     FB3_17  16    I/O     (b)
XLXI_46/PS0           7       2<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Dark                   8: XLXI_27/XLXI_68/Q<4>  15: XLXI_33/XLXI_9/Q<5> 
  2: Tilt                   9: XLXI_27/XLXI_68/Q<5>  16: XLXI_33/XLXI_9/Q<7> 
  3: Timer_in              10: XLXI_27/XLXI_68/Q<6>  17: XLXI_33/XLXI_9/XLXI_7/Q<6> 
  4: XLXI_27/XLXI_68/Q<0>  11: XLXI_27/XLXI_68/Q<7>  18: XLXI_46/PS0 
  5: XLXI_27/XLXI_68/Q<1>  12: XLXI_27/XLXN_340      19: XLXI_46/PS1 
  6: XLXI_27/XLXI_68/Q<2>  13: XLXI_27/XLXN_341      20: XLXI_46/PS2 
  7: XLXI_27/XLXI_68/Q<3>  14: XLXI_27/XLXN_342     

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LED7                 XX...................................... 2
XLXI_27/XLXI_97/XLXN_281 
                     ..X..................................... 1
XLXI_46/PS2          XX.XXXXXXXXXXX...XXX.................... 16
XLXI_33/XLXI_9/XLXI_7/Q<6> 
                     ..............X.XXXX.................... 5
XLXI_33/XLXI_9/Q<7>  ...............XXXXX.................... 5
XLXI_46/PS0          XX.XXXXXXXXXXX...XXX.................... 16
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   19    I/O     
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   20    I/O     
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   21    I/O     
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  22    I/O     
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  23    I/O     
(unused)              0       0     0   5     FB4_15  27    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  28    I/O     
(unused)              0       0     0   5     FB4_18        (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********














LED0 <= NOT (((NOT Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2)
	OR (XLXI_46/PS0 AND XLXI_46/PS1)
	OR (NOT XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(2) AND 
	XLXI_46/PS2)
	OR (XLXI_33/XLXI_9/Q(1) AND NOT XLXI_33/XLXI_9/Q(2) AND 
	XLXI_46/PS2)));


LED1 <= ((XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS1 AND Enable)
	OR (NOT XLXI_46/PS0 AND NOT XLXI_46/PS1 AND Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS1 AND Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS1 AND Enable));


LED2 <= ((NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1 AND 
	Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1 AND 
	Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1 AND 
	Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1 AND 
	Enable));


LED3 <= NOT (((NOT Enable)
	OR (EXP7_.EXP)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS1)));


LED4 <= ((NOT XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(2) AND 
	XLXI_46/PS2 AND NOT XLXI_46/PS0)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(2) AND 
	XLXI_46/PS2 AND NOT XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0)
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS1));


LED5 <= ((NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1));


LED6 <= NOT (((XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2)
	OR (XLXI_46/PS0 AND XLXI_46/PS1)
	OR (NOT XLXI_46/PS0 AND NOT XLXI_46/PS1)));


LED7 <= NOT ((Tilt AND Dark));


LM0 <= NOT (((NOT Enable)
	OR (XLXI_46/PS0 AND XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS1)));


LM1 <= ((NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1 AND 
	Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1 AND 
	Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1 AND 
	Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1 AND 
	Enable));


RM0 <= ((XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS1 AND Enable)
	OR (NOT XLXI_46/PS0 AND NOT XLXI_46/PS1 AND Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS1 AND Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND Enable)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	NOT XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2 AND NOT XLXI_46/PS1 AND Enable));


RM1 <= NOT (((NOT Enable)
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1) AND 
	XLXI_33/XLXI_9/Q(2) AND XLXI_46/PS2)
	OR (XLXI_46/PS0 AND XLXI_46/PS1)
	OR (NOT XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(2) AND 
	XLXI_46/PS2)
	OR (XLXI_33/XLXI_9/Q(1) AND NOT XLXI_33/XLXI_9/Q(2) AND 
	XLXI_46/PS2)));

FTCPE_XLXI_27/XLXI_68/Q0: FTCPE port map (XLXI_27/XLXI_68/Q(0),XLXI_27/XLXI_68/Q_T(0),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(0) <= ((XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_68/Q1: FTCPE port map (XLXI_27/XLXI_68/Q(1),XLXI_27/XLXI_68/Q_T(1),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(1) <= ((XLXI_27/XLXI_68/Q(1) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(1) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND NOT XLXI_46/PS0 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_68/Q2: FTCPE port map (XLXI_27/XLXI_68/Q(2),XLXI_27/XLXI_68/Q_T(2),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(2) <= ((XLXI_27/XLXI_68/Q(2) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(2) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(1) AND 
	NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(1) AND 
	XLXI_46/PS2 AND XLXI_46/PS1 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_68/Q3: FTCPE port map (XLXI_27/XLXI_68/Q(3),XLXI_27/XLXI_68/Q_T(3),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(3) <= ((XLXI_27/XLXI_68/Q(3) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(3) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(1) AND 
	XLXI_27/XLXI_68/Q(2) AND NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(1) AND 
	XLXI_27/XLXI_68/Q(2) AND XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_68/Q4: FTCPE port map (XLXI_27/XLXI_68/Q(4),XLXI_27/XLXI_68/Q_T(4),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(4) <= ((XLXI_27/XLXI_68/Q(4) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(4) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(1) AND 
	XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(3) AND NOT XLXI_46/PS0 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(1) AND 
	XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(3) AND XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_68/Q5: FTCPE port map (XLXI_27/XLXI_68/Q(5),XLXI_27/XLXI_68/Q_T(5),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(5) <= ((XLXI_27/XLXI_68/Q(5) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(5) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(3) AND 
	NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(3) AND 
	XLXI_46/PS2 AND XLXI_46/PS1 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_68/Q6: FTCPE port map (XLXI_27/XLXI_68/Q(6),XLXI_27/XLXI_68/Q_T(6),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(6) <= ((XLXI_27/XLXI_68/Q(6) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(6) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(3) AND NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(3) AND XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_68/Q7: FTCPE port map (XLXI_27/XLXI_68/Q(7),XLXI_27/XLXI_68/Q_T(7),CLK,NOT CLR,'0');
XLXI_27/XLXI_68/Q_T(7) <= ((XLXI_27/XLXI_68/Q(7) AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(7) AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND NOT XLXI_46/PS0 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXI_96/Q0: FTCPE port map (XLXI_27/XLXI_96/Q0,XLXI_27/XLXI_96/Q0_T,CLK,NOT CLR,'0');
XLXI_27/XLXI_96/Q0_T <= ((XLXI_27/XLXI_96/Q0 AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXI_96/Q0 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	XLXI_46/PS2 AND XLXI_46/PS1 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282));

FDCPE_XLXI_27/XLXI_97/XLXN_281: FDCPE port map (XLXI_27/XLXI_97/XLXN_281,Timer_in,CLK,NOT CLR,'0');

FDCPE_XLXI_27/XLXI_97/XLXN_282: FDCPE port map (XLXI_27/XLXI_97/XLXN_282,XLXI_27/XLXI_97/XLXN_281,CLK,NOT CLR,'0');

FTCPE_XLXI_27/XLXN_340: FTCPE port map (XLXI_27/XLXN_340,XLXI_27/XLXN_340_T,CLK,NOT CLR,'0');
XLXI_27/XLXN_340_T <= ((XLXI_27/XLXN_340 AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXN_340 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_96/Q0 AND 
	XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND 
	XLXI_27/XLXI_68/Q(7) AND NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_96/Q0 AND 
	XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND 
	XLXI_27/XLXI_68/Q(7) AND XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXN_341: FTCPE port map (XLXI_27/XLXN_341,XLXI_27/XLXN_341_T,CLK,NOT CLR,'0');
XLXI_27/XLXN_341_T <= ((XLXI_27/XLXN_341 AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXN_341 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_96/Q0 AND 
	XLXI_27/XLXN_340 AND XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(6) AND 
	XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND NOT XLXI_46/PS0 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_96/Q0 AND 
	XLXI_27/XLXN_340 AND XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(6) AND 
	XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND XLXI_46/PS2 AND XLXI_46/PS1 AND 
	XLXI_27/XLXI_97/XLXN_281 AND NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_27/XLXN_342: FTCPE port map (XLXI_27/XLXN_342,XLXI_27/XLXN_342_T,CLK,NOT CLR,'0');
XLXI_27/XLXN_342_T <= ((XLXI_27/XLXN_342 AND NOT XLXI_46/PS2 AND XLXI_46/PS0)
	OR (XLXI_27/XLXN_342 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_96/Q0 AND 
	XLXI_27/XLXN_340 AND XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(6) AND 
	XLXI_27/XLXN_341 AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	NOT XLXI_46/PS0 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_96/Q0 AND 
	XLXI_27/XLXN_340 AND XLXI_27/XLXI_68/Q(2) AND XLXI_27/XLXI_68/Q(6) AND 
	XLXI_27/XLXN_341 AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	XLXI_46/PS2 AND XLXI_46/PS1 AND XLXI_27/XLXI_97/XLXN_281 AND 
	NOT XLXI_27/XLXI_97/XLXN_282));

FTCPE_XLXI_33/XLXI_9/Q0: FTCPE port map (XLXI_33/XLXI_9/Q(0),XLXI_33/XLXI_9/Q_T(0),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/Q_T(0) <= ((NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5) AND NOT XLXI_33/XLXI_9/Q(7))
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	XLXI_33/XLXI_9/Q(4) AND NOT XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/Q(7))
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	NOT XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/Q(7))
	OR (NOT XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	NOT XLXI_33/XLXI_9/Q(4) AND NOT XLXI_33/XLXI_9/Q(5) AND NOT XLXI_33/XLXI_9/Q(7))
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(3) AND 
	XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/Q(7))
	OR (LED6_OBUF.EXP)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	NOT XLXI_33/XLXI_9/Q(4) AND NOT XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/Q(7))
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(3) AND 
	XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5) AND NOT XLXI_33/XLXI_9/Q(7))
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(3) AND 
	XLXI_33/XLXI_9/Q(4) AND NOT XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/Q(7))
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(3) AND 
	NOT XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/Q(7))
	OR (XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(3) AND 
	NOT XLXI_33/XLXI_9/Q(4) AND NOT XLXI_33/XLXI_9/Q(5) AND NOT XLXI_33/XLXI_9/Q(7))
	OR (XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/Q(7))
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	XLXI_33/XLXI_9/Q(4) AND NOT XLXI_33/XLXI_9/Q(5) AND NOT XLXI_33/XLXI_9/Q(7))
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(3) AND 
	NOT XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5) AND NOT XLXI_33/XLXI_9/Q(7)));

FTCPE_XLXI_33/XLXI_9/Q1: FTCPE port map (XLXI_33/XLXI_9/Q(1),XLXI_33/XLXI_9/Q_T(1),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/Q_T(1) <= ((XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(0) AND XLXI_33/XLXI_9/Q(1))
	OR (NOT XLXI_33/XLXI_9/Q(0) AND NOT XLXI_33/XLXI_9/Q(1)));

FTCPE_XLXI_33/XLXI_9/Q2: FTCPE port map (XLXI_33/XLXI_9/Q(2),XLXI_33/XLXI_9/Q_T(2),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/Q_T(2) <= ((XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(1) AND XLXI_33/XLXI_9/Q(2))
	OR (NOT XLXI_33/XLXI_9/Q(1) AND NOT XLXI_33/XLXI_9/Q(2)));

FTCPE_XLXI_33/XLXI_9/Q3: FTCPE port map (XLXI_33/XLXI_9/Q(3),XLXI_33/XLXI_9/Q_T(3),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/Q_T(3) <= ((XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (XLXI_33/XLXI_9/Q(2) AND XLXI_33/XLXI_9/Q(3))
	OR (NOT XLXI_33/XLXI_9/Q(2) AND NOT XLXI_33/XLXI_9/Q(3))
	OR (XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1));

FTCPE_XLXI_33/XLXI_9/Q4: FTCPE port map (XLXI_33/XLXI_9/Q(4),XLXI_33/XLXI_9/Q_T(4),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/Q_T(4) <= ((XLXI_33/XLXI_9/Q(3) AND XLXI_33/XLXI_9/Q(4))
	OR (NOT XLXI_33/XLXI_9/Q(3) AND NOT XLXI_33/XLXI_9/Q(4))
	OR (XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1));

FTCPE_XLXI_33/XLXI_9/Q5: FTCPE port map (XLXI_33/XLXI_9/Q(5),XLXI_33/XLXI_9/Q_T(5),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/Q_T(5) <= ((XLXI_33/XLXI_9/Q(4) AND XLXI_33/XLXI_9/Q(5))
	OR (NOT XLXI_33/XLXI_9/Q(4) AND NOT XLXI_33/XLXI_9/Q(5))
	OR (XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1));

FTCPE_XLXI_33/XLXI_9/Q7: FTCPE port map (XLXI_33/XLXI_9/Q(7),XLXI_33/XLXI_9/Q_T(7),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/Q_T(7) <= ((XLXI_33/XLXI_9/Q(7) AND XLXI_33/XLXI_9/XLXI_7/Q(6))
	OR (NOT XLXI_33/XLXI_9/Q(7) AND NOT XLXI_33/XLXI_9/XLXI_7/Q(6))
	OR (XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1));

FTCPE_XLXI_33/XLXI_9/XLXI_7/Q6: FTCPE port map (XLXI_33/XLXI_9/XLXI_7/Q(6),XLXI_33/XLXI_9/XLXI_7/Q_T(6),CLK,NOT CLR,'0');
XLXI_33/XLXI_9/XLXI_7/Q_T(6) <= ((XLXI_33/XLXI_9/Q(5) AND XLXI_33/XLXI_9/XLXI_7/Q(6))
	OR (NOT XLXI_33/XLXI_9/Q(5) AND NOT XLXI_33/XLXI_9/XLXI_7/Q(6))
	OR (XLXI_46/PS2 AND XLXI_46/PS0 AND NOT XLXI_46/PS1)
	OR (XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1));

FDCPE_XLXI_46/PS0: FDCPE port map (XLXI_46/PS0,XLXI_46/PS0_D,CLK,NOT CLR,'0');
XLXI_46/PS0_D <= ((XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1 AND NOT Dark)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1 AND NOT Tilt)
	OR (NOT XLXI_46/PS2 AND NOT XLXI_46/PS0 AND NOT XLXI_46/PS1 AND NOT Tilt)
	OR (NOT XLXI_46/PS2 AND NOT XLXI_46/PS0 AND NOT XLXI_46/PS1 AND NOT Dark)
	OR (XLXI_27/XLXN_340 AND NOT XLXI_27/XLXN_341 AND 
	NOT XLXI_27/XLXN_342 AND NOT XLXI_46/PS2 AND NOT XLXI_46/PS0 AND XLXI_46/PS1)
	OR (XLXI_27/XLXN_340 AND NOT XLXI_27/XLXN_341 AND 
	NOT XLXI_27/XLXN_342 AND NOT XLXI_46/PS0 AND NOT XLXI_46/PS1 AND NOT Tilt)
	OR (XLXI_27/XLXN_340 AND NOT XLXI_27/XLXN_341 AND 
	NOT XLXI_27/XLXN_342 AND NOT XLXI_46/PS0 AND NOT XLXI_46/PS1 AND NOT Dark));

FTCPE_XLXI_46/PS1: FTCPE port map (XLXI_46/PS1,XLXI_46/PS1_T,CLK,NOT CLR,'0');
XLXI_46/PS1_T <= ((XLXI_46/PS0)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	XLXI_46/PS2 AND XLXI_46/PS1 AND Tilt AND Dark));

FTCPE_XLXI_46/PS2: FTCPE port map (XLXI_46/PS2,XLXI_46/PS2_T,CLK,NOT CLR,'0');
XLXI_46/PS2_T <= ((XLXI_46/PS0 AND XLXI_46/PS1)
	OR (XLXI_27/XLXN_340 AND NOT XLXI_27/XLXN_341 AND 
	NOT XLXI_27/XLXN_342 AND XLXI_46/PS2 AND NOT XLXI_46/PS0 AND NOT XLXI_46/PS1 AND Tilt AND 
	Dark)
	OR (XLXI_27/XLXI_68/Q(0) AND XLXI_27/XLXI_68/Q(4) AND 
	XLXI_27/XLXI_68/Q(1) AND XLXI_27/XLXI_68/Q(5) AND XLXI_27/XLXI_68/Q(2) AND 
	XLXI_27/XLXI_68/Q(6) AND XLXI_27/XLXI_68/Q(3) AND XLXI_27/XLXI_68/Q(7) AND 
	XLXI_46/PS2 AND XLXI_46/PS1));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC9572XL-5-VQ44     29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 LED4                             23 KPR                           
  2 LED5                             24 TDO                           
  3 LED6                             25 GND                           
  4 GND                              26 VCC                           
  5 LED7                             27 KPR                           
  6 KPR                              28 KPR                           
  7 Tilt                             29 KPR                           
  8 KPR                              30 KPR                           
  9 TDI                              31 Dark                          
 10 TMS                              32 Timer_in                      
 11 TCK                              33 CLR                           
 12 KPR                              34 RM1                           
 13 KPR                              35 VCC                           
 14 KPR                              36 RM0                           
 15 VCC                              37 LM1                           
 16 KPR                              38 LM0                           
 17 GND                              39 LED3                          
 18 Enable                           40 LED2                          
 19 KPR                              41 LED1                          
 20 KPR                              42 LED0                          
 21 KPR                              43 KPR                           
 22 KPR                              44 CLK                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
