 
cpldfit:  version P.40xd                            Xilinx Inc.
                                  Fitter Report
Design Name: obstacle                            Date:  8-31-2015,  4:45PM
Device Used: XC9572XL-5-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
11 /72  ( 15%) 36  /360  ( 10%) 24 /216 ( 11%)   6  /72  (  8%) 16 /34  ( 47%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           4/18        4/54        8/90       4/ 9
FB2           3/18        4/54        7/90       4/ 9
FB3           3/18        8/54       16/90       4/ 9
FB4           1/18        8/54        5/90       4/ 7
             -----       -----       -----      -----    
             11/72       24/216      36/360     16/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'clr' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    5           5    |  I/O              :    13      28
Output        :    9           9    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     1       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     16          16

** Power Data **

There are 11 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'obstacle.ise'.
*************************  Summary of Mapped Logic  ************************

** 9 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
cmd0                2     3     FB1_2   39   I/O     O       STD  FAST 
cmd2                2     3     FB1_6   41   I/O     O       STD  FAST 
start_timer         2     3     FB1_15  2    I/O     O       STD  FAST 
cmd1                3     3     FB2_2   29   I/O     O       STD  FAST 
valid               2     3     FB2_8   32   I/O     O       STD  FAST 
ps2                 5     8     FB3_9   8    I/O     O       STD  FAST RESET
update              2     3     FB3_14  13   I/O     O       STD  FAST RESET
ps0                 9     8     FB3_17  16   I/O     O       STD  FAST RESET
ps1                 5     8     FB4_5   20   I/O     O       STD  FAST RESET

** 2 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
XLXN_35             2     4     FB1_18  STD  RESET
XLXN_38             2     4     FB2_18  STD  RESET

** 7 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
clk                 FB1_9   43~  GCK/I/O GCK
clr                 FB2_9   33~  GSR/I/O GSR
left                FB2_11  34   GTS/I/O I
back                FB3_8   7    I/O     I
right               FB4_11  22   I/O     I
timer_finish        FB4_14  23   I/O     I
front               FB4_17  28   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               4/50
Number of signals used by logic mapping into function block:  4
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
cmd0                  2       0     0   3     FB1_2   39    I/O     O
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   40    I/O     
cmd2                  2       0     0   3     FB1_6   41    I/O     O
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   42    I/O     
(unused)              0       0     0   5     FB1_9   43    GCK/I/O GCK
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  44    GCK/I/O 
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  1     GCK/I/O 
start_timer           2       0     0   3     FB1_15  2     I/O     O
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  3     I/O     
XLXN_35               2       0     0   3     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ps0                3: ps2                4: right 
  2: ps1              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cmd0                 XXX..................................... 3
cmd2                 XXX..................................... 3
start_timer          XXX..................................... 3
XLXN_35              XXXX.................................... 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               4/50
Number of signals used by logic mapping into function block:  4
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
cmd1                  3       0     0   2     FB2_2   29    I/O     O
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   30    I/O     
(unused)              0       0     0   5     FB2_6   31    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
valid                 2       0     0   3     FB2_8   32    I/O     O
(unused)              0       0     0   5     FB2_9   33    GSR/I/O GSR
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  34    GTS/I/O I
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
(unused)              0       0     0   5     FB2_14  36    GTS/I/O 
(unused)              0       0     0   5     FB2_15  37    I/O     
(unused)              0       0     0   5     FB2_16        (b)     
(unused)              0       0     0   5     FB2_17  38    I/O     
XLXN_38               2       0     0   3     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: left               3: ps1                4: ps2 
  2: ps0              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cmd1                 .XXX.................................... 3
valid                .XXX.................................... 3
XLXN_38              XXXX.................................... 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               8/46
Number of signals used by logic mapping into function block:  8
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   5     I/O     
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   6     I/O     
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   7     I/O     I
ps2                   5       0     0   0     FB3_9   8     I/O     O
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  12    I/O     
(unused)              0       0     0   5     FB3_12        (b)     
(unused)              0       0     0   5     FB3_13        (b)     
update                2       0     0   3     FB3_14  13    I/O     O
(unused)              0       0     0   5     FB3_15  14    I/O     
(unused)              0       0   \/2   3     FB3_16  18    I/O     (b)
ps0                   9       4<-   0   0     FB3_17  16    I/O     O
(unused)              0       0   /\2   3     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: XLXN_35            4: front              7: ps2 
  2: XLXN_38            5: ps0                8: timer_finish 
  3: back               6: ps1              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ps2                  XXXXXXXX................................ 8
update               ....XXX................................. 3
ps0                  XXXXXXXX................................ 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               8/46
Number of signals used by logic mapping into function block:  8
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   19    I/O     
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
ps1                   5       0     0   0     FB4_5   20    I/O     O
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   21    I/O     
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  22    I/O     I
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  23    I/O     I
(unused)              0       0     0   5     FB4_15  27    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  28    I/O     I
(unused)              0       0     0   5     FB4_18        (b)     

Signals Used by Logic in Function Block
  1: XLXN_35            4: front              7: ps2 
  2: XLXN_38            5: ps0                8: timer_finish 
  3: back               6: ps1              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ps1                  XXXXXXXX................................ 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********





FDCPE_XLXN_35: FDCPE port map (XLXN_35,right,clk,clr,'0',XLXN_35_CE);
XLXN_35_CE <= (ps0 AND NOT ps2 AND NOT ps1);

FDCPE_XLXN_38: FDCPE port map (XLXN_38,left,clk,clr,'0',XLXN_38_CE);
XLXN_38_CE <= (ps0 AND NOT ps2 AND NOT ps1);


cmd0 <= ((NOT ps1)
	OR (ps0 AND NOT ps2));


cmd1 <= ((ps0 AND NOT ps1)
	OR (ps2 AND NOT ps1)
	OR (NOT ps0 AND NOT ps2 AND ps1));


cmd2 <= ((NOT ps0 AND ps2)
	OR (ps0 AND NOT ps2 AND NOT ps1));

FDCPE_ps0: FDCPE port map (ps0,ps0_D,clk,clr,'0');
ps0_D <= ((ps0 AND ps2 AND NOT ps1 AND NOT timer_finish AND NOT back)
	OR (NOT ps0 AND ps1 AND NOT timer_finish AND NOT front AND back)
	OR (NOT XLXN_35 AND XLXN_38 AND NOT ps0 AND ps2 AND NOT ps1)
	OR (NOT ps0 AND NOT ps2 AND NOT ps1 AND front AND NOT back)
	OR (NOT ps2 AND NOT ps1 AND NOT front AND back)
	OR (NOT ps2 AND NOT timer_finish AND NOT front AND back)
	OR (ps0 AND ps2 AND NOT ps1 AND NOT timer_finish AND NOT front)
	OR (ps0 AND NOT ps2 AND ps1 AND NOT timer_finish AND NOT back)
	OR (NOT ps0 AND ps1 AND NOT timer_finish AND front AND NOT back));

FDCPE_ps1: FDCPE port map (ps1,ps1_D,clk,clr,'0');
ps1_D <= ((XLXN_35 AND NOT XLXN_38 AND NOT ps0 AND ps2 AND NOT ps1)
	OR (ps0 AND NOT ps2 AND NOT ps1 AND front AND NOT back)
	OR (ps0 AND NOT ps2 AND NOT ps1 AND NOT front AND back)
	OR (NOT ps0 AND ps1 AND NOT timer_finish AND NOT front AND NOT back)
	OR (NOT ps2 AND ps1 AND NOT timer_finish AND NOT front AND NOT back));

FDCPE_ps2: FDCPE port map (ps2,ps2_D,clk,clr,'0');
ps2_D <= ((NOT ps2 AND ps1 AND timer_finish)
	OR (XLXN_35 AND NOT XLXN_38 AND NOT ps0 AND ps2 AND NOT ps1)
	OR (NOT XLXN_35 AND XLXN_38 AND NOT ps0 AND ps2 AND NOT ps1)
	OR (ps0 AND ps2 AND NOT ps1 AND NOT timer_finish AND NOT front AND NOT back)
	OR (NOT ps0 AND ps2 AND ps1 AND NOT timer_finish AND NOT front AND NOT back));


start_timer <= ((ps0 AND NOT ps2 AND NOT ps1)
	OR (NOT ps0 AND ps2 AND NOT ps1));

FDCPE_update: FDCPE port map (update,update_D,clk,clr,'0');
update_D <= ((ps0 AND NOT ps2 AND NOT ps1)
	OR (NOT ps0 AND ps2 AND NOT ps1));


valid <= NOT (((ps0 AND ps2 AND ps1)
	OR (NOT ps0 AND NOT ps2 AND NOT ps1)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC9572XL-5-VQ44     29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 timer_finish                  
  2 start_timer                      24 TDO                           
  3 KPR                              25 GND                           
  4 GND                              26 VCC                           
  5 KPR                              27 KPR                           
  6 KPR                              28 front                         
  7 back                             29 cmd1                          
  8 ps2                              30 KPR                           
  9 TDI                              31 KPR                           
 10 TMS                              32 valid                         
 11 TCK                              33 clr                           
 12 KPR                              34 left                          
 13 update                           35 VCC                           
 14 KPR                              36 KPR                           
 15 VCC                              37 KPR                           
 16 ps0                              38 KPR                           
 17 GND                              39 cmd0                          
 18 KPR                              40 KPR                           
 19 KPR                              41 cmd2                          
 20 ps1                              42 KPR                           
 21 KPR                              43 clk                           
 22 right                            44 KPR                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
