| Random Project Status (08/31/2015 - 13:49:38) | |||
| Project File: | Random.xise | Parser Errors: | No Errors |
| Module Name: | Random | Implementation State: | Fitted |
| Target Device: | xc9572xl-5VQ44 |
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No Errors |
| Product Version: | ISE 14.3 |
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2 Warnings (2 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mon Aug 31 13:49:18 2015 | 0 | 2 Warnings (2 new) | 3 Infos (3 new) | |
| Translation Report | Current | Mon Aug 31 13:49:25 2015 | 0 | 0 | 0 | |
| CPLD Fitter Report (Text) | Current | Mon Aug 31 13:49:28 2015 | 0 | 1 Warning (1 new) | 0 | |
| Power Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Mon Aug 31 13:48:59 2015 | |
| Post-Fit Simulation Model Report | |||