 
cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: wall_system                         Date: 10-16-2015,  4:19PM
Device Used: XC9572XL-5-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
41 /72  ( 57%) 88  /360  ( 24%) 47 /216 ( 22%)   34 /72  ( 47%) 13 /34  ( 38%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          18/18*      21/54       52/90       4/ 9
FB2           5/18        5/54        8/90       6/ 9
FB3          18/18*      21/54       28/90       1/ 9
FB4           0/18        0/54        0/90       2/ 7
             -----       -----       -----      -----    
             41/72       47/216      88/360     13/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Signal 'CLR' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :     9      28
Output        :    8           8    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     2       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     13          13

** Power Data **

There are 41 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'wall_system.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK' based upon the LOC
   constraint 'P44'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
*************************  Summary of Mapped Logic  ************************

** 8 Outputs **

Signal                   Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                     Pts   Inps          No.  Type    Use     Mode Rate State
LED2                     1     1     FB1_5   40   I/O     O       STD  FAST 
LED1                     1     1     FB1_6   41   I/O     O       STD  FAST 
LED0                     1     3     FB1_8   42   I/O     O       STD  FAST 
RM1                      1     2     FB2_11  34   GTS/I/O O       STD  FAST 
RM0                      3     4     FB2_14  36   GTS/I/O O       STD  FAST 
LM1                      1     2     FB2_15  37   I/O     O       STD  FAST 
LM0                      2     3     FB2_17  38   I/O     O       STD  FAST 
PWM_OUT                  3     5     FB3_5   6    I/O     O       STD  FAST RESET

** 33 Buried Nodes **

Signal                   Total Total Loc     Pwr  Reg Init
Name                     Pts   Inps          Mode State
XLXI_6/XLXI_8/Q<6>       1     6     FB1_1   STD  RESET
XLXI_6/XLXI_8/Q<5>       1     5     FB1_2   STD  RESET
XLXI_6/XLXI_8/Q<4>       1     4     FB1_3   STD  RESET
XLXI_5/XLXI_97/XLXN_282  1     1     FB1_4   STD  RESET
XLXI_12/XLXN_3           3     13    FB1_7   STD  RESET
XLXI_5/XLXI_68/Q<4>      4     10    FB1_9   STD  RESET
XLXI_5/XLXI_68/Q<3>      4     9     FB1_10  STD  RESET
XLXI_5/XLXI_68/Q<2>      4     8     FB1_11  STD  RESET
XLXI_5/XLXI_68/Q<1>      4     7     FB1_12  STD  RESET
XLXI_5/XLXI_68/Q<0>      4     6     FB1_13  STD  RESET
XLXI_5/Q<7>              4     13    FB1_14  STD  RESET
XLXI_5/Q<6>              4     12    FB1_15  STD  RESET
XLXI_5/Q<5>              4     11    FB1_16  STD  RESET
XLXI_12/XLXN_5           5     13    FB1_17  STD  RESET
XLXI_12/XLXN_4           5     13    FB1_18  STD  RESET
XLXI_6/XLXN_89           1     1     FB2_18  STD  RESET
XLXI_6/XLXN_96           1     1     FB3_1   STD  RESET
XLXI_6/XLXN_126          1     1     FB3_2   STD  RESET
XLXI_6/XLXN_124          0     0     FB3_3   STD  RESET
XLXI_6/XLXI_8/Q<9>       1     9     FB3_4   STD  RESET
XLXI_6/XLXI_8/Q<8>       1     8     FB3_6   STD  RESET
XLXI_6/XLXI_8/Q<7>       1     7     FB3_7   STD  RESET
XLXI_6/XLXI_8/Q<3>       1     3     FB3_8   STD  RESET
XLXI_6/XLXI_8/Q<2>       1     2     FB3_9   STD  RESET
XLXI_6/XLXI_8/Q<1>       1     1     FB3_10  STD  RESET
XLXI_6/XLXI_8/Q<0>       0     0     FB3_11  STD  RESET
XLXI_6/Q<10>             1     10    FB3_12  STD  RESET
XLXI_5/XLXI_97/XLXN_281  1     1     FB3_13  STD  RESET
XLXI_6/p3                3     5     FB3_14  STD  RESET
XLXI_6/p2                3     5     FB3_15  STD  RESET
XLXI_6/p1                3     5     FB3_16  STD  RESET
XLXI_6/p0                3     5     FB3_17  STD  RESET
XLXI_6/XLXN_161          3     5     FB3_18  STD  RESET

** 5 Inputs **

Signal                   Loc     Pin  Pin     Pin     
Name                             No.  Type    Use     
CLK                      FB1_11  44   GCK/I/O GCK
Timer_In                 FB2_8   32   I/O     I
CLR                      FB2_9   33   GSR/I/O GSR
IR0                      FB4_14  23   I/O     I
IR1                      FB4_15  27   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
XLXI_6/XLXI_8/Q<6>    1       0     0   4     FB1_1         (b)     (b)
XLXI_6/XLXI_8/Q<5>    1       0     0   4     FB1_2   39    I/O     (b)
XLXI_6/XLXI_8/Q<4>    1       0     0   4     FB1_3         (b)     (b)
XLXI_5/XLXI_97/XLXN_282
                      1       0     0   4     FB1_4         (b)     (b)
LED2                  1       0     0   4     FB1_5   40    I/O     O
LED1                  1       0     0   4     FB1_6   41    I/O     O
XLXI_12/XLXN_3        3       0     0   2     FB1_7         (b)     (b)
LED0                  1       0     0   4     FB1_8   42    I/O     O
XLXI_5/XLXI_68/Q<4>   4       0     0   1     FB1_9   43    GCK/I/O (b)
XLXI_5/XLXI_68/Q<3>   4       0     0   1     FB1_10        (b)     (b)
XLXI_5/XLXI_68/Q<2>   4       0     0   1     FB1_11  44    GCK/I/O GCK
XLXI_5/XLXI_68/Q<1>   4       0     0   1     FB1_12        (b)     (b)
XLXI_5/XLXI_68/Q<0>   4       0     0   1     FB1_13        (b)     (b)
XLXI_5/Q<7>           4       0     0   1     FB1_14  1     GCK/I/O (b)
XLXI_5/Q<6>           4       0     0   1     FB1_15  2     I/O     (b)
XLXI_5/Q<5>           4       0     0   1     FB1_16        (b)     (b)
XLXI_12/XLXN_5        5       0     0   0     FB1_17  3     I/O     (b)
XLXI_12/XLXN_4        5       0     0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: IR0                8: XLXI_5/Q<7>              15: XLXI_5/XLXI_97/XLXN_282 
  2: IR1                9: XLXI_5/XLXI_68/Q<0>      16: XLXI_6/XLXI_8/Q<0> 
  3: XLXI_12/XLXN_3    10: XLXI_5/XLXI_68/Q<1>      17: XLXI_6/XLXI_8/Q<1> 
  4: XLXI_12/XLXN_4    11: XLXI_5/XLXI_68/Q<2>      18: XLXI_6/XLXI_8/Q<2> 
  5: XLXI_12/XLXN_5    12: XLXI_5/XLXI_68/Q<3>      19: XLXI_6/XLXI_8/Q<3> 
  6: XLXI_5/Q<5>       13: XLXI_5/XLXI_68/Q<4>      20: XLXI_6/XLXI_8/Q<4> 
  7: XLXI_5/Q<6>       14: XLXI_5/XLXI_97/XLXN_281  21: XLXI_6/XLXI_8/Q<5> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_6/XLXI_8/Q<6>   ...............XXXXXX................... 6
XLXI_6/XLXI_8/Q<5>   ...............XXXXX.................... 5
XLXI_6/XLXI_8/Q<4>   ...............XXXX..................... 4
XLXI_5/XLXI_97/XLXN_282 
                     .............X.......................... 1
LED2                 .X...................................... 1
LED1                 X....................................... 1
XLXI_12/XLXN_3       XXXXXXXXXXXXX........................... 13
LED0                 ..XXX................................... 3
XLXI_5/XLXI_68/Q<4>  ..XXX...XXXXXXX......................... 10
XLXI_5/XLXI_68/Q<3>  ..XXX...XXXX.XX......................... 9
XLXI_5/XLXI_68/Q<2>  ..XXX...XXX..XX......................... 8
XLXI_5/XLXI_68/Q<1>  ..XXX...XX...XX......................... 7
XLXI_5/XLXI_68/Q<0>  ..XXX...X....XX......................... 6
XLXI_5/Q<7>          ..XXXXXXXXXXXXX......................... 13
XLXI_5/Q<6>          ..XXXXX.XXXXXXX......................... 12
XLXI_5/Q<5>          ..XXXX..XXXXXXX......................... 11
XLXI_12/XLXN_5       XXXXXXXXXXXXX........................... 13
XLXI_12/XLXN_4       XXXXXXXXXXXXX........................... 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               5/49
Number of signals used by logic mapping into function block:  5
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   29    I/O     
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   30    I/O     
(unused)              0       0     0   5     FB2_6   31    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   32    I/O     I
(unused)              0       0     0   5     FB2_9   33    GSR/I/O GSR
(unused)              0       0     0   5     FB2_10        (b)     
RM1                   1       0     0   4     FB2_11  34    GTS/I/O O
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
RM0                   3       0     0   2     FB2_14  36    GTS/I/O O
LM1                   1       0     0   4     FB2_15  37    I/O     O
(unused)              0       0     0   5     FB2_16        (b)     
LM0                   2       0     0   3     FB2_17  38    I/O     O
XLXI_6/XLXN_89        1       0     0   4     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: PWM_OUT            3: XLXI_12/XLXN_4     5: XLXI_6/Q<10> 
  2: XLXI_12/XLXN_3     4: XLXI_12/XLXN_5   

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
RM1                  .XX..................................... 2
RM0                  XXXX.................................... 4
LM1                  .XX..................................... 2
LM0                  XXX..................................... 3
XLXI_6/XLXN_89       ....X................................... 1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
XLXI_6/XLXN_96        1       0     0   4     FB3_1         (b)     (b)
XLXI_6/XLXN_126       1       0     0   4     FB3_2   5     I/O     (b)
XLXI_6/XLXN_124       0       0     0   5     FB3_3         (b)     (b)
XLXI_6/XLXI_8/Q<9>    1       0     0   4     FB3_4         (b)     (b)
PWM_OUT               3       0     0   2     FB3_5   6     I/O     O
XLXI_6/XLXI_8/Q<8>    1       0     0   4     FB3_6         (b)     (b)
XLXI_6/XLXI_8/Q<7>    1       0     0   4     FB3_7         (b)     (b)
XLXI_6/XLXI_8/Q<3>    1       0     0   4     FB3_8   7     I/O     (b)
XLXI_6/XLXI_8/Q<2>    1       0     0   4     FB3_9   8     I/O     (b)
XLXI_6/XLXI_8/Q<1>    1       0     0   4     FB3_10        (b)     (b)
XLXI_6/XLXI_8/Q<0>    0       0     0   5     FB3_11  12    I/O     (b)
XLXI_6/Q<10>          1       0     0   4     FB3_12        (b)     (b)
XLXI_5/XLXI_97/XLXN_281
                      1       0     0   4     FB3_13        (b)     (b)
XLXI_6/p3             3       0     0   2     FB3_14  13    I/O     (b)
XLXI_6/p2             3       0     0   2     FB3_15  14    I/O     (b)
XLXI_6/p1             3       0     0   2     FB3_16  18    I/O     (b)
XLXI_6/p0             3       0     0   2     FB3_17  16    I/O     (b)
XLXI_6/XLXN_161       3       0     0   2     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: PWM_OUT              8: XLXI_6/XLXI_8/Q<5>  15: XLXI_6/XLXN_161 
  2: Timer_In             9: XLXI_6/XLXI_8/Q<6>  16: XLXI_6/XLXN_89 
  3: XLXI_6/XLXI_8/Q<0>  10: XLXI_6/XLXI_8/Q<7>  17: XLXI_6/XLXN_96 
  4: XLXI_6/XLXI_8/Q<1>  11: XLXI_6/XLXI_8/Q<8>  18: XLXI_6/p0 
  5: XLXI_6/XLXI_8/Q<2>  12: XLXI_6/XLXI_8/Q<9>  19: XLXI_6/p1 
  6: XLXI_6/XLXI_8/Q<3>  13: XLXI_6/XLXN_124     20: XLXI_6/p2 
  7: XLXI_6/XLXI_8/Q<4>  14: XLXI_6/XLXN_126     21: XLXI_6/p3 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_6/XLXN_96       ...............X........................ 1
XLXI_6/XLXN_126      ............X........................... 1
XLXI_6/XLXN_124      ........................................ 0
XLXI_6/XLXI_8/Q<9>   ..XXXXXXXXX............................. 9
PWM_OUT              X............X.XX...X................... 5
XLXI_6/XLXI_8/Q<8>   ..XXXXXXXX.............................. 8
XLXI_6/XLXI_8/Q<7>   ..XXXXXXX............................... 7
XLXI_6/XLXI_8/Q<3>   ..XXX................................... 3
XLXI_6/XLXI_8/Q<2>   ..XX.................................... 2
XLXI_6/XLXI_8/Q<1>   ..X..................................... 1
XLXI_6/XLXI_8/Q<0>   ........................................ 0
XLXI_6/Q<10>         ..XXXXXXXXXX............................ 10
XLXI_5/XLXI_97/XLXN_281 
                     .X...................................... 1
XLXI_6/p3            .............XXXX...X................... 5
XLXI_6/p2            .............X.XX.XX.................... 5
XLXI_6/p1            .............X.XXXX..................... 5
XLXI_6/p0            X............X.XXX...................... 5
XLXI_6/XLXN_161      .............XXXX..X.................... 5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   19    I/O     
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   20    I/O     
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   21    I/O     
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  22    I/O     
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  23    I/O     I
(unused)              0       0     0   5     FB4_15  27    I/O     I
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  28    I/O     
(unused)              0       0     0   5     FB4_18        (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********


LED0 <= (NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND NOT XLXI_12/XLXN_5);


LED1 <= IR0;


LED2 <= IR1;


LM0 <= NOT (((XLXI_12/XLXN_4 AND XLXI_12/XLXN_3)
	OR (NOT PWM_OUT AND NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3)));


LM1 <= (XLXI_12/XLXN_4 AND XLXI_12/XLXN_3);

FDCPE_PWM_OUT: FDCPE port map (PWM_OUT,PWM_OUT_D,CLK,NOT CLR,'0');
PWM_OUT_D <= ((PWM_OUT AND XLXI_6/XLXN_126 AND NOT XLXI_6/XLXN_89)
	OR (PWM_OUT AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_96)
	OR (XLXI_6/p3 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_89 AND 
	NOT XLXI_6/XLXN_96));


RM0 <= NOT (((NOT XLXI_12/XLXN_4 AND XLXI_12/XLXN_3)
	OR (NOT PWM_OUT AND XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3)
	OR (NOT PWM_OUT AND NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_5)));


RM1 <= (NOT XLXI_12/XLXN_4 AND XLXI_12/XLXN_3);

FTCPE_XLXI_12/XLXN_3: FTCPE port map (XLXI_12/XLXN_3,XLXI_12/XLXN_3_T,CLK,NOT CLR,'0');
XLXI_12/XLXN_3_T <= ((XLXI_5/Q(5) AND NOT XLXI_5/Q(6) AND NOT XLXI_5/Q(7) AND 
	XLXI_12/XLXN_3 AND XLXI_12/XLXN_5)
	OR (NOT IR1 AND NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND 
	XLXI_12/XLXN_5 AND NOT IR0)
	OR (XLXI_5/Q(5) AND XLXI_5/XLXI_68/Q(0) AND 
	XLXI_5/XLXI_68/Q(4) AND XLXI_5/Q(6) AND XLXI_5/XLXI_68/Q(1) AND XLXI_5/Q(7) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND IR1 AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_3 AND XLXI_12/XLXN_5));

FTCPE_XLXI_12/XLXN_4: FTCPE port map (XLXI_12/XLXN_4,XLXI_12/XLXN_4_T,CLK,NOT CLR,'0');
XLXI_12/XLXN_4_T <= ((IR1 AND NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND IR0)
	OR (NOT IR1 AND XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND 
	XLXI_12/XLXN_5)
	OR (NOT IR1 AND NOT XLXI_12/XLXN_3 AND XLXI_12/XLXN_5 AND NOT IR0)
	OR (XLXI_5/Q(5) AND NOT XLXI_5/Q(6) AND NOT XLXI_5/Q(7) AND 
	XLXI_12/XLXN_4 AND XLXI_12/XLXN_3 AND XLXI_12/XLXN_5)
	OR (XLXI_5/Q(5) AND XLXI_5/XLXI_68/Q(0) AND 
	XLXI_5/XLXI_68/Q(4) AND XLXI_5/Q(6) AND XLXI_5/XLXI_68/Q(1) AND XLXI_5/Q(7) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_3 AND XLXI_12/XLXN_5));

FDCPE_XLXI_12/XLXN_5: FDCPE port map (XLXI_12/XLXN_5,XLXI_12/XLXN_5_D,CLK,NOT CLR,'0');
XLXI_12/XLXN_5_D <= ((IR1 AND NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3)
	OR (NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND NOT IR0)
	OR (NOT IR1 AND NOT XLXI_12/XLXN_3 AND XLXI_12/XLXN_5 AND NOT IR0)
	OR (XLXI_5/Q(5) AND NOT XLXI_5/Q(6) AND NOT XLXI_5/Q(7) AND 
	XLXI_12/XLXN_4 AND XLXI_12/XLXN_3 AND XLXI_12/XLXN_5)
	OR (XLXI_5/Q(5) AND XLXI_5/XLXI_68/Q(0) AND 
	XLXI_5/XLXI_68/Q(4) AND XLXI_5/Q(6) AND XLXI_5/XLXI_68/Q(1) AND XLXI_5/Q(7) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_3 AND XLXI_12/XLXN_5));

FTCPE_XLXI_5/Q5: FTCPE port map (XLXI_5/Q(5),XLXI_5/Q_T(5),CLK,NOT CLR,'0');
XLXI_5/Q_T(5) <= ((XLXI_5/Q(5) AND XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_5)
	OR (XLXI_5/Q(5) AND XLXI_12/XLXN_3 AND NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(4) AND 
	XLXI_5/XLXI_68/Q(1) AND XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND 
	XLXI_12/XLXN_5 AND XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(4) AND 
	XLXI_5/XLXI_68/Q(1) AND XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND 
	NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND XLXI_5/XLXI_97/XLXN_281 AND 
	NOT XLXI_5/XLXI_97/XLXN_282));

FTCPE_XLXI_5/Q6: FTCPE port map (XLXI_5/Q(6),XLXI_5/Q_T(6),CLK,NOT CLR,'0');
XLXI_5/Q_T(6) <= ((XLXI_5/Q(6) AND XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_5)
	OR (XLXI_5/Q(6) AND XLXI_12/XLXN_3 AND NOT XLXI_12/XLXN_5)
	OR (XLXI_5/Q(5) AND XLXI_5/XLXI_68/Q(0) AND 
	XLXI_5/XLXI_68/Q(4) AND XLXI_5/XLXI_68/Q(1) AND XLXI_5/XLXI_68/Q(2) AND 
	XLXI_5/XLXI_68/Q(3) AND XLXI_12/XLXN_5 AND XLXI_5/XLXI_97/XLXN_281 AND 
	NOT XLXI_5/XLXI_97/XLXN_282)
	OR (XLXI_5/Q(5) AND XLXI_5/XLXI_68/Q(0) AND 
	XLXI_5/XLXI_68/Q(4) AND XLXI_5/XLXI_68/Q(1) AND XLXI_5/XLXI_68/Q(2) AND 
	XLXI_5/XLXI_68/Q(3) AND NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND 
	XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282));

FTCPE_XLXI_5/Q7: FTCPE port map (XLXI_5/Q(7),XLXI_5/Q_T(7),CLK,NOT CLR,'0');
XLXI_5/Q_T(7) <= ((XLXI_5/Q(7) AND XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_5)
	OR (XLXI_5/Q(7) AND XLXI_12/XLXN_3 AND NOT XLXI_12/XLXN_5)
	OR (XLXI_5/Q(5) AND XLXI_5/XLXI_68/Q(0) AND 
	XLXI_5/XLXI_68/Q(4) AND XLXI_5/Q(6) AND XLXI_5/XLXI_68/Q(1) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND XLXI_12/XLXN_5 AND 
	XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282)
	OR (XLXI_5/Q(5) AND XLXI_5/XLXI_68/Q(0) AND 
	XLXI_5/XLXI_68/Q(4) AND XLXI_5/Q(6) AND XLXI_5/XLXI_68/Q(1) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND NOT XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_3 AND XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282));

FTCPE_XLXI_5/XLXI_68/Q0: FTCPE port map (XLXI_5/XLXI_68/Q(0),XLXI_5/XLXI_68/Q_T(0),CLK,NOT CLR,'0');
XLXI_5/XLXI_68/Q_T(0) <= ((XLXI_5/XLXI_68/Q(0) AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_12/XLXN_3 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_12/XLXN_5 AND XLXI_5/XLXI_97/XLXN_281 AND 
	NOT XLXI_5/XLXI_97/XLXN_282)
	OR (NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND 
	XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282));

FTCPE_XLXI_5/XLXI_68/Q1: FTCPE port map (XLXI_5/XLXI_68/Q(1),XLXI_5/XLXI_68/Q_T(1),CLK,NOT CLR,'0');
XLXI_5/XLXI_68/Q_T(1) <= ((XLXI_5/XLXI_68/Q(1) AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(1) AND XLXI_12/XLXN_3 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_12/XLXN_5 AND 
	XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282)
	OR (XLXI_5/XLXI_68/Q(0) AND NOT XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_3 AND XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282));

FTCPE_XLXI_5/XLXI_68/Q2: FTCPE port map (XLXI_5/XLXI_68/Q(2),XLXI_5/XLXI_68/Q_T(2),CLK,NOT CLR,'0');
XLXI_5/XLXI_68/Q_T(2) <= ((XLXI_5/XLXI_68/Q(2) AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(2) AND XLXI_12/XLXN_3 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(1) AND 
	XLXI_12/XLXN_5 AND XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(1) AND 
	NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND XLXI_5/XLXI_97/XLXN_281 AND 
	NOT XLXI_5/XLXI_97/XLXN_282));

FTCPE_XLXI_5/XLXI_68/Q3: FTCPE port map (XLXI_5/XLXI_68/Q(3),XLXI_5/XLXI_68/Q_T(3),CLK,NOT CLR,'0');
XLXI_5/XLXI_68/Q_T(3) <= ((XLXI_5/XLXI_68/Q(3) AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(3) AND XLXI_12/XLXN_3 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(1) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_12/XLXN_5 AND XLXI_5/XLXI_97/XLXN_281 AND 
	NOT XLXI_5/XLXI_97/XLXN_282)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(1) AND 
	XLXI_5/XLXI_68/Q(2) AND NOT XLXI_12/XLXN_4 AND NOT XLXI_12/XLXN_3 AND 
	XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282));

FTCPE_XLXI_5/XLXI_68/Q4: FTCPE port map (XLXI_5/XLXI_68/Q(4),XLXI_5/XLXI_68/Q_T(4),CLK,NOT CLR,'0');
XLXI_5/XLXI_68/Q_T(4) <= ((XLXI_5/XLXI_68/Q(4) AND XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(4) AND XLXI_12/XLXN_3 AND 
	NOT XLXI_12/XLXN_5)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(1) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND XLXI_12/XLXN_5 AND 
	XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282)
	OR (XLXI_5/XLXI_68/Q(0) AND XLXI_5/XLXI_68/Q(1) AND 
	XLXI_5/XLXI_68/Q(2) AND XLXI_5/XLXI_68/Q(3) AND NOT XLXI_12/XLXN_4 AND 
	NOT XLXI_12/XLXN_3 AND XLXI_5/XLXI_97/XLXN_281 AND NOT XLXI_5/XLXI_97/XLXN_282));

FDCPE_XLXI_5/XLXI_97/XLXN_281: FDCPE port map (XLXI_5/XLXI_97/XLXN_281,Timer_In,CLK,NOT CLR,'0');

FDCPE_XLXI_5/XLXI_97/XLXN_282: FDCPE port map (XLXI_5/XLXI_97/XLXN_282,XLXI_5/XLXI_97/XLXN_281,CLK,NOT CLR,'0');

FTCPE_XLXI_6/Q10: FTCPE port map (XLXI_6/Q(10),XLXI_6/Q_T(10),CLK,NOT CLR,'0');
XLXI_6/Q_T(10) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(4) AND 
	XLXI_6/XLXI_8/Q(1) AND XLXI_6/XLXI_8/Q(5) AND XLXI_6/XLXI_8/Q(2) AND 
	XLXI_6/XLXI_8/Q(6) AND XLXI_6/XLXI_8/Q(8) AND XLXI_6/XLXI_8/Q(3) AND 
	XLXI_6/XLXI_8/Q(7) AND XLXI_6/XLXI_8/Q(9));

FTCPE_XLXI_6/XLXI_8/Q0: FTCPE port map (XLXI_6/XLXI_8/Q(0),'1',CLK,NOT CLR,'0');

FTCPE_XLXI_6/XLXI_8/Q1: FTCPE port map (XLXI_6/XLXI_8/Q(1),XLXI_6/XLXI_8/Q(0),CLK,NOT CLR,'0');

FTCPE_XLXI_6/XLXI_8/Q2: FTCPE port map (XLXI_6/XLXI_8/Q(2),XLXI_6/XLXI_8/Q_T(2),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(2) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(1));

FTCPE_XLXI_6/XLXI_8/Q3: FTCPE port map (XLXI_6/XLXI_8/Q(3),XLXI_6/XLXI_8/Q_T(3),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(3) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(1) AND 
	XLXI_6/XLXI_8/Q(2));

FTCPE_XLXI_6/XLXI_8/Q4: FTCPE port map (XLXI_6/XLXI_8/Q(4),XLXI_6/XLXI_8/Q_T(4),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(4) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(1) AND 
	XLXI_6/XLXI_8/Q(2) AND XLXI_6/XLXI_8/Q(3));

FTCPE_XLXI_6/XLXI_8/Q5: FTCPE port map (XLXI_6/XLXI_8/Q(5),XLXI_6/XLXI_8/Q_T(5),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(5) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(4) AND 
	XLXI_6/XLXI_8/Q(1) AND XLXI_6/XLXI_8/Q(2) AND XLXI_6/XLXI_8/Q(3));

FTCPE_XLXI_6/XLXI_8/Q6: FTCPE port map (XLXI_6/XLXI_8/Q(6),XLXI_6/XLXI_8/Q_T(6),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(6) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(4) AND 
	XLXI_6/XLXI_8/Q(1) AND XLXI_6/XLXI_8/Q(5) AND XLXI_6/XLXI_8/Q(2) AND 
	XLXI_6/XLXI_8/Q(3));

FTCPE_XLXI_6/XLXI_8/Q7: FTCPE port map (XLXI_6/XLXI_8/Q(7),XLXI_6/XLXI_8/Q_T(7),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(7) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(4) AND 
	XLXI_6/XLXI_8/Q(1) AND XLXI_6/XLXI_8/Q(5) AND XLXI_6/XLXI_8/Q(2) AND 
	XLXI_6/XLXI_8/Q(6) AND XLXI_6/XLXI_8/Q(3));

FTCPE_XLXI_6/XLXI_8/Q8: FTCPE port map (XLXI_6/XLXI_8/Q(8),XLXI_6/XLXI_8/Q_T(8),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(8) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(4) AND 
	XLXI_6/XLXI_8/Q(1) AND XLXI_6/XLXI_8/Q(5) AND XLXI_6/XLXI_8/Q(2) AND 
	XLXI_6/XLXI_8/Q(6) AND XLXI_6/XLXI_8/Q(3) AND XLXI_6/XLXI_8/Q(7));

FTCPE_XLXI_6/XLXI_8/Q9: FTCPE port map (XLXI_6/XLXI_8/Q(9),XLXI_6/XLXI_8/Q_T(9),CLK,NOT CLR,'0');
XLXI_6/XLXI_8/Q_T(9) <= (XLXI_6/XLXI_8/Q(0) AND XLXI_6/XLXI_8/Q(4) AND 
	XLXI_6/XLXI_8/Q(1) AND XLXI_6/XLXI_8/Q(5) AND XLXI_6/XLXI_8/Q(2) AND 
	XLXI_6/XLXI_8/Q(6) AND XLXI_6/XLXI_8/Q(8) AND XLXI_6/XLXI_8/Q(3) AND 
	XLXI_6/XLXI_8/Q(7));

FDCPE_XLXI_6/XLXN_124: FDCPE port map (XLXI_6/XLXN_124,'1',CLK,NOT CLR,'0');

FDCPE_XLXI_6/XLXN_126: FDCPE port map (XLXI_6/XLXN_126,XLXI_6/XLXN_124,CLK,NOT CLR,'0');

FDCPE_XLXI_6/XLXN_161: FDCPE port map (XLXI_6/XLXN_161,XLXI_6/XLXN_161_D,CLK,NOT CLR,'0');
XLXI_6/XLXN_161_D <= ((NOT XLXI_6/XLXN_161 AND XLXI_6/XLXN_126 AND 
	NOT XLXI_6/XLXN_89)
	OR (NOT XLXI_6/XLXN_161 AND XLXI_6/XLXN_126 AND 
	XLXI_6/XLXN_96)
	OR (NOT XLXI_6/p2 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_89 AND 
	NOT XLXI_6/XLXN_96));

FDCPE_XLXI_6/XLXN_89: FDCPE port map (XLXI_6/XLXN_89,XLXI_6/Q(10),CLK,NOT CLR,'0');

FDCPE_XLXI_6/XLXN_96: FDCPE port map (XLXI_6/XLXN_96,XLXI_6/XLXN_89,CLK,NOT CLR,'0');

FDCPE_XLXI_6/p0: FDCPE port map (XLXI_6/p0,XLXI_6/p0_D,CLK,NOT CLR,'0');
XLXI_6/p0_D <= ((NOT XLXI_6/p0 AND XLXI_6/XLXN_126 AND NOT XLXI_6/XLXN_89)
	OR (NOT XLXI_6/p0 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_96)
	OR (NOT PWM_OUT AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_89 AND 
	NOT XLXI_6/XLXN_96));

FDCPE_XLXI_6/p1: FDCPE port map (XLXI_6/p1,XLXI_6/p1_D,CLK,NOT CLR,'0');
XLXI_6/p1_D <= ((NOT XLXI_6/p1 AND XLXI_6/XLXN_126 AND NOT XLXI_6/XLXN_89)
	OR (NOT XLXI_6/p1 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_96)
	OR (NOT XLXI_6/p0 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_89 AND 
	NOT XLXI_6/XLXN_96));

FDCPE_XLXI_6/p2: FDCPE port map (XLXI_6/p2,XLXI_6/p2_D,CLK,NOT CLR,'0');
XLXI_6/p2_D <= ((NOT XLXI_6/p2 AND XLXI_6/XLXN_126 AND NOT XLXI_6/XLXN_89)
	OR (NOT XLXI_6/p2 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_96)
	OR (NOT XLXI_6/p1 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_89 AND 
	NOT XLXI_6/XLXN_96));

FDCPE_XLXI_6/p3: FDCPE port map (XLXI_6/p3,XLXI_6/p3_D,CLK,NOT CLR,'0');
XLXI_6/p3_D <= ((XLXI_6/p3 AND XLXI_6/XLXN_126 AND NOT XLXI_6/XLXN_89)
	OR (XLXI_6/p3 AND XLXI_6/XLXN_126 AND XLXI_6/XLXN_96)
	OR (XLXI_6/XLXN_161 AND XLXI_6/XLXN_126 AND 
	XLXI_6/XLXN_89 AND NOT XLXI_6/XLXN_96));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC9572XL-5-VQ44     29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 IR0                           
  2 KPR                              24 TDO                           
  3 KPR                              25 GND                           
  4 GND                              26 VCC                           
  5 KPR                              27 IR1                           
  6 PWM_OUT                          28 KPR                           
  7 KPR                              29 KPR                           
  8 KPR                              30 KPR                           
  9 TDI                              31 KPR                           
 10 TMS                              32 Timer_In                      
 11 TCK                              33 CLR                           
 12 KPR                              34 RM1                           
 13 KPR                              35 VCC                           
 14 KPR                              36 RM0                           
 15 VCC                              37 LM1                           
 16 KPR                              38 LM0                           
 17 GND                              39 KPR                           
 18 KPR                              40 LED2                          
 19 KPR                              41 LED1                          
 20 KPR                              42 LED0                          
 21 KPR                              43 KPR                           
 22 KPR                              44 CLK                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
