 
cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: explore                             Date:  9-25-2015,  2:48PM
Device Used: XC9572XL-5-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
40 /72  ( 56%) 289 /360  ( 80%) 99 /216 ( 46%)   28 /72  ( 39%) 18 /34  ( 53%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          10/18       24/54       81/90       8/ 9
FB2          10/18       26/54       82/90       6/ 9
FB3           7/18       27/54       81/90       0/ 9
FB4          13/18       22/54       45/90       4/ 7
             -----       -----       -----      -----    
             40/72       99/216     289/360     18/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Signal 'CLR' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    5           5    |  I/O              :    13      28
Output        :   11          11    |  GCK/IO           :     2       3
Bidirectional :    0           0    |  GTS/IO           :     2       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     18          18

** Power Data **

There are 40 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'explore.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK' based upon the LOC
   constraint 'P44'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
*************************  Summary of Mapped Logic  ************************

** 11 Outputs **

Signal                        Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                          Pts   Inps          No.  Type    Use     Mode Rate State
LED3                          10    9     FB1_2   39   I/O     O       STD  FAST 
LED2                          9     9     FB1_5   40   I/O     O       STD  FAST 
LED1                          10    9     FB1_6   41   I/O     O       STD  FAST 
LED0                          9     9     FB1_8   42   I/O     O       STD  FAST 
LED4                          2     3     FB1_14  1    GCK/I/O O       STD  FAST 
LED5                          2     4     FB1_15  2    I/O     O       STD  FAST 
LED6                          1     2     FB1_17  3    I/O     O       STD  FAST 
RM1                           9     9     FB2_11  34   GTS/I/O O       STD  FAST 
RM0                           10    9     FB2_14  36   GTS/I/O O       STD  FAST 
LM1                           9     9     FB2_15  37   I/O     O       STD  FAST 
LM0                           10    9     FB2_17  38   I/O     O       STD  FAST 

** 29 Buried Nodes **

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
XLXI_70/XLXI_68/Q<4>          11    17    FB1_13  STD  RESET
XLXI_70/XLXI_68/Q<6>          13    19    FB1_16  STD  RESET
XLXI_70/XLXI_68/Q<7>          14    20    FB1_18  STD  RESET
XLXI_70/XLXI_68/Q<5>          12    18    FB2_2   STD  RESET
XLXI_70/XLXI_68/Q<3>          10    16    FB2_5   STD  RESET
XLXI_70/XLXI_68/Q<2>          9     15    FB2_6   STD  RESET
XLXI_70/XLXI_68/Q<1>          8     14    FB2_8   STD  RESET
Blocked_inst/ps2              3     13    FB2_9   STD  RESET
Blocked_inst/cnt0             2     4     FB2_10  STD  RESET
Blocked_inst/ps0              6     16    FB3_2   STD  RESET
Loop_inst/PS2                 8     9     FB3_7   STD  RESET
Loop_inst/PS3                 9     17    FB3_9   STD  RESET
Loop_inst/PS1                 11    17    FB3_11  STD  RESET
Obstacle_inst/ps2             13    17    FB3_12  STD  RESET
Obstacle_inst/ps1             13    17    FB3_16  STD  RESET
Obstacle_inst/ps0             21    17    FB3_18  STD  RESET
Loop_inst/PS0                 10    9     FB4_2   STD  RESET
XLXI_70/XLXN_282              1     1     FB4_6   STD  RESET
XLXI_70/XLXN_281              1     1     FB4_7   STD  RESET
update                        2     3     FB4_8   STD  RESET
looping_dir                   2     3     FB4_9   STD  RESET
Obstacle_inst/XLXN_38         2     5     FB4_10  STD  RESET
Obstacle_inst/XLXN_35         2     5     FB4_11  STD  RESET
$OpTx$$OpTx$FX_DC$55_INV$203  2     4     FB4_12  STD  
Random_inst/Q0                3     6     FB4_13  STD  RESET
Random_inst/Q1                4     7     FB4_14  STD  RESET
Blocked_inst/cnt1             4     5     FB4_15  STD  RESET
Blocked_inst/ps1              5     8     FB4_16  STD  RESET
XLXI_70/XLXI_68/Q<0>          7     13    FB4_18  STD  RESET

** 7 Inputs **

Signal                        Loc     Pin  Pin     Pin     
Name                                  No.  Type    Use     
CLK                           FB1_11  44   GCK/I/O GCK
Timer_In                      FB2_8   32   I/O     I
CLR                           FB2_9   33   GSR/I/O GSR
FL                            FB4_2   19   I/O     I
FR                            FB4_5   20   I/O     I
BL                            FB4_8   21   I/O     I
BR                            FB4_11  22   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               24/30
Number of signals used by logic mapping into function block:  24
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB1_1         (b)     (b)
LED3                 10      10<- /\5   0     FB1_2   39    I/O     O
(unused)              0       0   /\5   0     FB1_3         (b)     (b)
(unused)              0       0   /\5   0     FB1_4         (b)     (b)
LED2                  9       4<-   0   0     FB1_5   40    I/O     O
LED1                 10       9<- /\4   0     FB1_6   41    I/O     O
(unused)              0       0   /\5   0     FB1_7         (b)     (b)
LED0                  9       8<- /\4   0     FB1_8   42    I/O     O
(unused)              0       0   /\5   0     FB1_9   43    GCK/I/O (b)
(unused)              0       0   /\3   2     FB1_10        (b)     (b)
(unused)              0       0     0   5     FB1_11  44    GCK/I/O GCK
(unused)              0       0   \/3   2     FB1_12        (b)     (b)
XLXI_70/XLXI_68/Q<4>
                     11       6<-   0   0     FB1_13        (b)     (b)
LED4                  2       0   /\3   0     FB1_14  1     GCK/I/O O
LED5                  2       0   \/3   0     FB1_15  2     I/O     O
XLXI_70/XLXI_68/Q<6>
                     13       8<-   0   0     FB1_16        (b)     (b)
LED6                  1       1<- /\5   0     FB1_17  3     I/O     O
XLXI_70/XLXI_68/Q<7>
                     14      10<- /\1   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$$OpTx$FX_DC$55_INV$203   9: Obstacle_inst/ps0     17: XLXI_70/XLXI_68/Q<3> 
  2: Blocked_inst/ps0              10: Obstacle_inst/ps1     18: XLXI_70/XLXI_68/Q<4> 
  3: Blocked_inst/ps1              11: Obstacle_inst/ps2     19: XLXI_70/XLXI_68/Q<5> 
  4: Blocked_inst/ps2              12: Random_inst/Q0        20: XLXI_70/XLXI_68/Q<6> 
  5: Loop_inst/PS0                 13: Random_inst/Q1        21: XLXI_70/XLXI_68/Q<7> 
  6: Loop_inst/PS1                 14: XLXI_70/XLXI_68/Q<0>  22: XLXI_70/XLXN_281 
  7: Loop_inst/PS2                 15: XLXI_70/XLXI_68/Q<1>  23: XLXI_70/XLXN_282 
  8: Loop_inst/PS3                 16: XLXI_70/XLXI_68/Q<2>  24: looping_dir 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LED3                 X.XX....XXXXX..........X................ 9
LED2                 X.XX....XXXXX..........X................ 9
LED1                 X.XX....XXXXX..........X................ 9
LED0                 X.XX....XXXXX..........X................ 9
XLXI_70/XLXI_68/Q<4> 
                     .XXXXXXXXXX..XXXXX...XX................. 17
LED4                 ........XXX............................. 3
LED5                 ....XXXX................................ 4
XLXI_70/XLXI_68/Q<6> 
                     .XXXXXXXXXX..XXXXXXX.XX................. 19
LED6                 ..XX.................................... 2
XLXI_70/XLXI_68/Q<7> 
                     .XXXXXXXXXX..XXXXXXXXXX................. 20
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/2   3     FB2_1         (b)     (b)
XLXI_70/XLXI_68/Q<5>
                     12       7<-   0   0     FB2_2   29    I/O     (b)
(unused)              0       0   /\5   0     FB2_3         (b)     (b)
(unused)              0       0   \/5   0     FB2_4         (b)     (b)
XLXI_70/XLXI_68/Q<3>
                     10       5<-   0   0     FB2_5   30    I/O     (b)
XLXI_70/XLXI_68/Q<2>
                      9       4<-   0   0     FB2_6   31    I/O     (b)
(unused)              0       0   /\4   1     FB2_7         (b)     (b)
XLXI_70/XLXI_68/Q<1>
                      8       3<-   0   0     FB2_8   32    I/O     I
Blocked_inst/ps2      3       1<- /\3   0     FB2_9   33    GSR/I/O GSR
Blocked_inst/cnt0     2       0   /\1   2     FB2_10        (b)     (b)
RM1                   9       4<-   0   0     FB2_11  34    GTS/I/O O
(unused)              0       0   /\4   1     FB2_12        (b)     (b)
(unused)              0       0   \/5   0     FB2_13        (b)     (b)
RM0                  10       5<-   0   0     FB2_14  36    GTS/I/O O
LM1                   9       4<-   0   0     FB2_15  37    I/O     O
(unused)              0       0   /\4   1     FB2_16        (b)     (b)
LM0                  10       5<-   0   0     FB2_17  38    I/O     O
(unused)              0       0   /\5   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$$OpTx$FX_DC$55_INV$203  10: Loop_inst/PS3         19: XLXI_70/XLXI_68/Q<3> 
  2: Blocked_inst/cnt0             11: Obstacle_inst/ps0     20: XLXI_70/XLXI_68/Q<4> 
  3: Blocked_inst/cnt1             12: Obstacle_inst/ps1     21: XLXI_70/XLXI_68/Q<5> 
  4: Blocked_inst/ps0              13: Obstacle_inst/ps2     22: XLXI_70/XLXI_68/Q<6> 
  5: Blocked_inst/ps1              14: Random_inst/Q0        23: XLXI_70/XLXI_68/Q<7> 
  6: Blocked_inst/ps2              15: Random_inst/Q1        24: XLXI_70/XLXN_281 
  7: Loop_inst/PS0                 16: XLXI_70/XLXI_68/Q<0>  25: XLXI_70/XLXN_282 
  8: Loop_inst/PS1                 17: XLXI_70/XLXI_68/Q<1>  26: looping_dir 
  9: Loop_inst/PS2                 18: XLXI_70/XLXI_68/Q<2> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_70/XLXI_68/Q<5> 
                     ...XXXXXXXXXX..XXXXXX..XX............... 18
XLXI_70/XLXI_68/Q<3> 
                     ...XXXXXXXXXX..XXXX....XX............... 16
XLXI_70/XLXI_68/Q<2> 
                     ...XXXXXXXXXX..XXX.....XX............... 15
XLXI_70/XLXI_68/Q<1> 
                     ...XXXXXXXXXX..XX......XX............... 14
Blocked_inst/ps2     .XXXXX.........XXXXXXXX................. 13
Blocked_inst/cnt0    .X.XXX.................................. 4
RM1                  X...XX....XXXXX..........X.............. 9
RM0                  X...XX....XXXXX..........X.............. 9
LM1                  X...XX....XXXXX..........X.............. 9
LM0                  X...XX....XXXXX..........X.............. 9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               27/27
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB3_1         (b)     (b)
Blocked_inst/ps0      6       5<- /\4   0     FB3_2   5     I/O     (b)
(unused)              0       0   /\5   0     FB3_3         (b)     (b)
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0   \/1   4     FB3_5   6     I/O     (b)
(unused)              0       0   \/5   0     FB3_6         (b)     (b)
Loop_inst/PS2         8       6<- \/3   0     FB3_7         (b)     (b)
(unused)              0       0   \/5   0     FB3_8   7     I/O     (b)
Loop_inst/PS3         9       8<- \/4   0     FB3_9   8     I/O     (b)
(unused)              0       0   \/5   0     FB3_10        (b)     (b)
Loop_inst/PS1        11       9<- \/3   0     FB3_11  12    I/O     (b)
Obstacle_inst/ps2    13       8<-   0   0     FB3_12        (b)     (b)
(unused)              0       0   /\5   0     FB3_13        (b)     (b)
(unused)              0       0   \/5   0     FB3_14  13    I/O     (b)
(unused)              0       0   \/5   0     FB3_15  14    I/O     (b)
Obstacle_inst/ps1    13      10<- \/2   0     FB3_16  18    I/O     (b)
(unused)              0       0   \/5   0     FB3_17  16    I/O     (b)
Obstacle_inst/ps0    21      16<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: BL                 10: Loop_inst/PS0          19: XLXI_70/XLXI_68/Q<0> 
  2: BR                 11: Loop_inst/PS1          20: XLXI_70/XLXI_68/Q<1> 
  3: Blocked_inst/cnt0  12: Loop_inst/PS2          21: XLXI_70/XLXI_68/Q<2> 
  4: Blocked_inst/cnt1  13: Loop_inst/PS3          22: XLXI_70/XLXI_68/Q<3> 
  5: Blocked_inst/ps0   14: Obstacle_inst/XLXN_35  23: XLXI_70/XLXI_68/Q<4> 
  6: Blocked_inst/ps1   15: Obstacle_inst/XLXN_38  24: XLXI_70/XLXI_68/Q<5> 
  7: Blocked_inst/ps2   16: Obstacle_inst/ps0      25: XLXI_70/XLXI_68/Q<6> 
  8: FL                 17: Obstacle_inst/ps1      26: XLXI_70/XLXI_68/Q<7> 
  9: FR                 18: Obstacle_inst/ps2      27: update 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
Blocked_inst/ps0     XXXXXXX...........XXXXXXXXX............. 16
Loop_inst/PS2        XX.....XXXXXX.............X............. 9
Loop_inst/PS3        XX.....XXXXXX.....XXXXXXXXX............. 17
Loop_inst/PS1        XX.....XXXXXX.....XXXXXXXXX............. 17
Obstacle_inst/ps2    XX.....XX....XXXXXXXXXXXXX.............. 17
Obstacle_inst/ps1    XX.....XX....XXXXXXXXXXXXX.............. 17
Obstacle_inst/ps0    XX.....XX....XXXXXXXXXXXXX.............. 17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               22/32
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB4_1         (b)     (b)
Loop_inst/PS0        10       5<-   0   0     FB4_2   19    I/O     I
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   20    I/O     I
XLXI_70/XLXN_282      1       0     0   4     FB4_6         (b)     (b)
XLXI_70/XLXN_281      1       0     0   4     FB4_7         (b)     (b)
update                2       0     0   3     FB4_8   21    I/O     I
looping_dir           2       0     0   3     FB4_9         (b)     (b)
Obstacle_inst/XLXN_38
                      2       0     0   3     FB4_10        (b)     (b)
Obstacle_inst/XLXN_35
                      2       0     0   3     FB4_11  22    I/O     I
$OpTx$$OpTx$FX_DC$55_INV$203
                      2       0     0   3     FB4_12        (b)     (b)
Random_inst/Q0        3       0     0   2     FB4_13        (b)     (b)
Random_inst/Q1        4       0     0   1     FB4_14  23    I/O     (b)
Blocked_inst/cnt1     4       0     0   1     FB4_15  27    I/O     (b)
Blocked_inst/ps1      5       0     0   0     FB4_16        (b)     (b)
(unused)              0       0   \/2   3     FB4_17  28    I/O     (b)
XLXI_70/XLXI_68/Q<0>
                      7       2<-   0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: BL                  9: FR                 16: Obstacle_inst/ps2 
  2: BR                 10: Loop_inst/PS0      17: Random_inst/Q0 
  3: Blocked_inst/cnt0  11: Loop_inst/PS1      18: Timer_In 
  4: Blocked_inst/cnt1  12: Loop_inst/PS2      19: XLXI_70/XLXI_68/Q<0> 
  5: Blocked_inst/ps0   13: Loop_inst/PS3      20: XLXI_70/XLXN_281 
  6: Blocked_inst/ps1   14: Obstacle_inst/ps0  21: XLXI_70/XLXN_282 
  7: Blocked_inst/ps2   15: Obstacle_inst/ps1  22: update 
  8: FL                

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
Loop_inst/PS0        XX.....XXXXXX........X.................. 9
XLXI_70/XLXN_282     ...................X.................... 1
XLXI_70/XLXN_281     .................X...................... 1
update               .............XXX........................ 3
looping_dir          X......X.............X.................. 3
Obstacle_inst/XLXN_38 
                     X......X.....XXX........................ 5
Obstacle_inst/XLXN_35 
                     .X......X....XXX........................ 5
$OpTx$$OpTx$FX_DC$55_INV$203 
                     .........XXXX........................... 4
Random_inst/Q0       .....XX..XXXX........................... 6
Random_inst/Q1       .....XX..XXXX...X....................... 7
Blocked_inst/cnt1    ..XXXXX................................. 5
Blocked_inst/ps1     ..XXXXXXX............X.................. 8
XLXI_70/XLXI_68/Q<0> 
                     ....XXX..XXXXXXX..XXX................... 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$$OpTx$FX_DC$55_INV$203 <= ((Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (NOT Loop_inst/PS0 AND Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3));

FTCPE_Blocked_inst/cnt0: FTCPE port map (Blocked_inst/cnt0,Blocked_inst/cnt0_T,CLK,NOT CLR,'0',Blocked_inst/cnt0_CE);
Blocked_inst/cnt0_T <= (NOT Blocked_inst/cnt0 AND NOT Blocked_inst/ps0 AND 
	NOT Blocked_inst/ps1 AND NOT Blocked_inst/ps2);
Blocked_inst/cnt0_CE <= (NOT Blocked_inst/ps1 AND NOT Blocked_inst/ps2);

FDCPE_Blocked_inst/cnt1: FDCPE port map (Blocked_inst/cnt1,Blocked_inst/cnt1_D,CLK,NOT CLR,'0',Blocked_inst/cnt1_CE);
Blocked_inst/cnt1_D <= ((Blocked_inst/cnt0 AND Blocked_inst/cnt1)
	OR (NOT Blocked_inst/cnt0 AND NOT Blocked_inst/cnt1)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	NOT Blocked_inst/ps2));
Blocked_inst/cnt1_CE <= (NOT Blocked_inst/ps1 AND NOT Blocked_inst/ps2);

FDCPE_Blocked_inst/ps0: FDCPE port map (Blocked_inst/ps0,Blocked_inst/ps0_D,CLK,NOT CLR,'0');
Blocked_inst/ps0_D <= ((update AND Blocked_inst/ps0 AND Blocked_inst/ps1)
	OR (NOT update AND NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps2)
	OR (BR AND BL AND NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps2)
	OR (Blocked_inst/cnt0 AND Blocked_inst/cnt1 AND 
	Blocked_inst/ps0 AND Blocked_inst/ps1)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXI_68/Q(2) AND 
	XLXI_70/XLXI_68/Q(6) AND XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXI_68/Q(7) AND 
	Blocked_inst/ps0 AND Blocked_inst/ps2)
	OR (Blocked_inst/ps1 AND Blocked_inst/ps2));

FDCPE_Blocked_inst/ps1: FDCPE port map (Blocked_inst/ps1,Blocked_inst/ps1_D,CLK,NOT CLR,'0');
Blocked_inst/ps1_D <= ((Blocked_inst/ps2)
	OR (update AND NOT Blocked_inst/ps0)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1)
	OR (FR AND FL AND update AND Blocked_inst/ps1)
	OR (Blocked_inst/cnt0 AND Blocked_inst/cnt1 AND 
	Blocked_inst/ps0 AND Blocked_inst/ps1));

FTCPE_Blocked_inst/ps2: FTCPE port map (Blocked_inst/ps2,Blocked_inst/ps2_T,CLK,NOT CLR,'0');
Blocked_inst/ps2_T <= ((XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXI_68/Q(2) AND 
	XLXI_70/XLXI_68/Q(6) AND XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXI_68/Q(7) AND 
	Blocked_inst/ps0 AND Blocked_inst/ps2)
	OR (Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (Blocked_inst/cnt0 AND Blocked_inst/cnt1 AND 
	Blocked_inst/ps0 AND Blocked_inst/ps1));
























































LED0 <= ((EXP11_.EXP)
	OR (NOT Random_inst/Q0 AND NOT looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND NOT looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps1 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps1 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203));


LED1 <= ((LED0_OBUF.EXP)
	OR (NOT Obstacle_inst/ps1 AND NOT Blocked_inst/ps2 AND 
	NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Random_inst/Q0 AND NOT looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps1 AND Blocked_inst/ps1 AND 
	NOT $OpTx$$OpTx$FX_DC$55_INV$203));


LED2 <= ((NOT Random_inst/Q0 AND NOT Random_inst/Q1 AND 
	NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (NOT Random_inst/Q0 AND looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1 AND Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1 AND NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203));


LED3 <= NOT (((EXP8_.EXP)
	OR (Random_inst/Q0 AND NOT looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)));


LED4 <= NOT (((Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)));


LED5 <= ((Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (NOT Loop_inst/PS0 AND Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3));


LED6 <= (NOT Blocked_inst/ps1 AND Blocked_inst/ps2);


LM0 <= NOT (((Random_inst/Q0 AND Random_inst/Q1 AND 
	NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (Random_inst/Q0 AND NOT looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND NOT Random_inst/Q1 AND 
	NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (NOT Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1 AND Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1 AND NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Random_inst/Q0 AND NOT looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)));


LM1 <= ((NOT Random_inst/Q0 AND NOT Random_inst/Q1 AND 
	NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (NOT Random_inst/Q0 AND looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1 AND Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1 AND NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203));

FDCPE_Loop_inst/PS0: FDCPE port map (Loop_inst/PS0,Loop_inst/PS0_D,CLK,NOT CLR,'0');
Loop_inst/PS0_D <= ((NOT FR AND FL AND BL AND NOT Loop_inst/PS0 AND update AND 
	NOT Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (NOT BR AND FL AND BL AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND 
	update AND NOT Loop_inst/PS3)
	OR (NOT BR AND FL AND BL AND NOT Loop_inst/PS0 AND update AND 
	NOT Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (FR AND BR AND NOT FL AND NOT Loop_inst/PS0 AND Loop_inst/PS1 AND 
	update AND Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (FR AND BR AND NOT BL AND NOT Loop_inst/PS0 AND Loop_inst/PS1 AND 
	update AND Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (Loop_inst/PS0 AND NOT update AND NOT Loop_inst/PS3)
	OR (FR AND BR AND FL AND BL AND Loop_inst/PS0 AND 
	NOT Loop_inst/PS3)
	OR (FR AND BR AND NOT FL AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND 
	update AND NOT Loop_inst/PS2)
	OR (FR AND BR AND NOT BL AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND 
	update AND NOT Loop_inst/PS2)
	OR (NOT FR AND FL AND BL AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND 
	update AND NOT Loop_inst/PS3));

FTCPE_Loop_inst/PS1: FTCPE port map (Loop_inst/PS1,Loop_inst/PS1_T,CLK,NOT CLR,'0');
Loop_inst/PS1_T <= ((Loop_inst/PS3.EXP)
	OR (NOT FR AND Loop_inst/PS1 AND update AND Loop_inst/PS2)
	OR (NOT BR AND Loop_inst/PS1 AND update AND Loop_inst/PS2)
	OR (NOT FL AND Loop_inst/PS1 AND update AND NOT Loop_inst/PS2 AND 
	NOT Loop_inst/PS3)
	OR (NOT BL AND Loop_inst/PS1 AND update AND NOT Loop_inst/PS2 AND 
	NOT Loop_inst/PS3)
	OR (NOT FR AND FL AND BL AND Loop_inst/PS0 AND update AND 
	NOT Loop_inst/PS2)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS2 AND Loop_inst/PS3)
	OR (Loop_inst/PS1 AND Loop_inst/PS2 AND Loop_inst/PS3));

FDCPE_Loop_inst/PS2: FDCPE port map (Loop_inst/PS2,Loop_inst/PS2_D,CLK,NOT CLR,'0');
Loop_inst/PS2_D <= ((EXP23_.EXP)
	OR (FR AND BR AND Loop_inst/PS0 AND NOT Loop_inst/PS1 AND 
	Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (FR AND BR AND NOT Loop_inst/PS0 AND Loop_inst/PS1 AND 
	Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (FR AND BR AND NOT FL AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND 
	update AND NOT Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (NOT FR AND FL AND BL AND Loop_inst/PS0 AND Loop_inst/PS1 AND 
	update AND NOT Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (NOT BR AND FL AND BL AND Loop_inst/PS0 AND Loop_inst/PS1 AND 
	update AND NOT Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (NOT update AND Loop_inst/PS2 AND NOT Loop_inst/PS3)
	OR (FR AND BR AND FL AND BL AND Loop_inst/PS2 AND 
	NOT Loop_inst/PS3));

FTCPE_Loop_inst/PS3: FTCPE port map (Loop_inst/PS3,Loop_inst/PS3_T,CLK,NOT CLR,'0');
Loop_inst/PS3_T <= ((Loop_inst/PS2.EXP)
	OR (Loop_inst/PS0 AND Loop_inst/PS1 AND Loop_inst/PS3)
	OR (NOT FR AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND update AND 
	Loop_inst/PS3)
	OR (NOT BR AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND update AND 
	Loop_inst/PS3)
	OR (FR AND BR AND NOT FL AND Loop_inst/PS0 AND Loop_inst/PS1 AND 
	update AND Loop_inst/PS2)
	OR (NOT FR AND FL AND BL AND NOT Loop_inst/PS0 AND NOT Loop_inst/PS1 AND 
	update AND Loop_inst/PS2)
	OR (Loop_inst/PS2 AND Loop_inst/PS3));

FDCPE_Obstacle_inst/XLXN_35: FDCPE port map (Obstacle_inst/XLXN_35,Obstacle_inst/XLXN_35_D,CLK,NOT CLR,'0',Obstacle_inst/XLXN_35_CE);
Obstacle_inst/XLXN_35_D <= (FR AND BR);
Obstacle_inst/XLXN_35_CE <= (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1);

FDCPE_Obstacle_inst/XLXN_38: FDCPE port map (Obstacle_inst/XLXN_38,Obstacle_inst/XLXN_38_D,CLK,NOT CLR,'0',Obstacle_inst/XLXN_38_CE);
Obstacle_inst/XLXN_38_D <= (FL AND BL);
Obstacle_inst/XLXN_38_CE <= (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1);

FDCPE_Obstacle_inst/ps0: FDCPE port map (Obstacle_inst/ps0,Obstacle_inst/ps0_D,CLK,NOT CLR,'0');
Obstacle_inst/ps0_D <= ((Blocked_inst/ps0.EXP)
	OR (NOT FR AND NOT BR AND NOT Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1)
	OR (NOT FR AND NOT BL AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT FR AND NOT BL AND NOT Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1)
	OR (NOT BR AND NOT FL AND NOT Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1)
	OR (NOT FL AND NOT BL AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (Obstacle_inst/ps1.EXP)
	OR (Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1)
	OR (NOT FR AND NOT BR AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT BR AND NOT FL AND Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1)
	OR (NOT BR AND NOT FL AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT FL AND NOT BL AND Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1)
	OR (NOT FR AND NOT BR AND Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1)
	OR (NOT FR AND NOT BL AND Obstacle_inst/ps0 AND NOT Obstacle_inst/ps1)
	OR (BR AND BL AND Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (FR AND BR AND FL AND BL AND Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1)
	OR (FR AND BR AND FL AND BL AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1));

FTCPE_Obstacle_inst/ps1: FTCPE port map (Obstacle_inst/ps1,Obstacle_inst/ps1_T,CLK,NOT CLR,'0');
Obstacle_inst/ps1_T <= ((EXP28_.EXP)
	OR (NOT FR AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT FL AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT FR AND BR AND BL AND Obstacle_inst/ps0 AND 
	NOT Obstacle_inst/ps2)
	OR (BR AND NOT FL AND BL AND Obstacle_inst/ps0 AND 
	NOT Obstacle_inst/ps2)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXI_68/Q(2) AND 
	XLXI_70/XLXI_68/Q(6) AND XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXI_68/Q(7) AND 
	Obstacle_inst/ps1)
	OR (NOT BR AND NOT Obstacle_inst/ps0 AND Obstacle_inst/ps1)
	OR (NOT BL AND NOT Obstacle_inst/ps0 AND Obstacle_inst/ps1)
	OR (Obstacle_inst/XLXN_35 AND NOT Obstacle_inst/XLXN_38 AND 
	NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1));

FTCPE_Obstacle_inst/ps2: FTCPE port map (Obstacle_inst/ps2,Obstacle_inst/ps2_T,CLK,NOT CLR,'0');
Obstacle_inst/ps2_T <= ((NOT FL AND Obstacle_inst/ps0 AND Obstacle_inst/ps2)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXI_68/Q(2) AND 
	XLXI_70/XLXI_68/Q(6) AND XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXI_68/Q(7) AND 
	Obstacle_inst/ps1)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXI_68/Q(2) AND 
	XLXI_70/XLXI_68/Q(6) AND XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXI_68/Q(7) AND 
	Obstacle_inst/ps0 AND Obstacle_inst/ps2)
	OR (NOT FR AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT BR AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT FL AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (NOT BL AND Obstacle_inst/ps2 AND Obstacle_inst/ps1)
	OR (Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	Obstacle_inst/ps1)
	OR (NOT FR AND Obstacle_inst/ps0 AND Obstacle_inst/ps2)
	OR (NOT BR AND Obstacle_inst/ps0 AND Obstacle_inst/ps2)
	OR (NOT BL AND Obstacle_inst/ps0 AND Obstacle_inst/ps2)
	OR (Obstacle_inst/XLXN_35 AND Obstacle_inst/XLXN_38 AND 
	NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/XLXN_35 AND NOT Obstacle_inst/XLXN_38 AND 
	NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND NOT Obstacle_inst/ps1));


RM0 <= ((Random_inst/Q0 AND Random_inst/Q1 AND 
	NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (Random_inst/Q0 AND NOT looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND NOT Random_inst/Q1 AND 
	NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (NOT Random_inst/Q0 AND looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps1 AND Blocked_inst/ps1 AND 
	NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps1 AND NOT Blocked_inst/ps2 AND 
	NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Random_inst/Q0 AND NOT looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203));


RM1 <= ((NOT Random_inst/Q0 AND Random_inst/Q1 AND 
	NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (NOT Random_inst/Q0 AND NOT looping_dir AND NOT Blocked_inst/ps2 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1 AND Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1 AND NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Random_inst/Q0 AND NOT looping_dir AND Blocked_inst/ps1 AND 
	$OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps1 AND 
	Blocked_inst/ps1 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps1 AND 
	NOT Blocked_inst/ps2 AND NOT $OpTx$$OpTx$FX_DC$55_INV$203));

FTCPE_Random_inst/Q0: FTCPE port map (Random_inst/Q0,Random_inst/Q0_T,CLK,NOT CLR,'0');
Random_inst/Q0_T <= ((NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (NOT Loop_inst/PS0 AND Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3));

FTCPE_Random_inst/Q1: FTCPE port map (Random_inst/Q1,Random_inst/Q1_T,CLK,NOT CLR,'0');
Random_inst/Q1_T <= ((NOT Random_inst/Q0)
	OR (NOT Blocked_inst/ps1 AND Blocked_inst/ps2)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (NOT Loop_inst/PS0 AND Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3));

FDCPE_XLXI_70/XLXI_68/Q0: FDCPE port map (XLXI_70/XLXI_68/Q(0),XLXI_70/XLXI_68/Q_D(0),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(0) <= ((XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXN_281 AND 
	NOT XLXI_70/XLXN_282)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXN_281)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXN_282)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	Blocked_inst/ps2));

FDCPE_XLXI_70/XLXI_68/Q1: FDCPE port map (XLXI_70/XLXI_68/Q(1),XLXI_70/XLXI_68/Q_D(1),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(1) <= ((NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(1) AND 
	XLXI_70/XLXN_281 AND NOT XLXI_70/XLXN_282)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXI_68/Q(1))
	OR (NOT XLXI_70/XLXI_68/Q(1) AND NOT XLXI_70/XLXN_281)
	OR (NOT XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXN_282)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	Blocked_inst/ps2));

FDCPE_XLXI_70/XLXI_68/Q2: FDCPE port map (XLXI_70/XLXI_68/Q(2),XLXI_70/XLXI_68/Q_D(2),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(2) <= ((Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(1) AND 
	XLXI_70/XLXI_68/Q(2) AND XLXI_70/XLXN_281 AND NOT XLXI_70/XLXN_282)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXI_68/Q(2))
	OR (NOT XLXI_70/XLXI_68/Q(1) AND NOT XLXI_70/XLXI_68/Q(2))
	OR (NOT XLXI_70/XLXI_68/Q(2) AND NOT XLXI_70/XLXN_281)
	OR (NOT XLXI_70/XLXI_68/Q(2) AND XLXI_70/XLXN_282)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	Blocked_inst/ps2));

FDCPE_XLXI_70/XLXI_68/Q3: FDCPE port map (XLXI_70/XLXI_68/Q(3),XLXI_70/XLXI_68/Q_D(3),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(3) <= ((Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	Blocked_inst/ps2)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(1) AND 
	XLXI_70/XLXI_68/Q(2) AND XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXN_281 AND 
	NOT XLXI_70/XLXN_282)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXI_68/Q(3))
	OR (NOT XLXI_70/XLXI_68/Q(1) AND NOT XLXI_70/XLXI_68/Q(3))
	OR (NOT XLXI_70/XLXI_68/Q(2) AND NOT XLXI_70/XLXI_68/Q(3))
	OR (NOT XLXI_70/XLXI_68/Q(3) AND NOT XLXI_70/XLXN_281)
	OR (NOT XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXN_282));

FDCPE_XLXI_70/XLXI_68/Q4: FDCPE port map (XLXI_70/XLXI_68/Q(4),XLXI_70/XLXI_68/Q_D(4),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(4) <= ((NOT XLXI_70/XLXI_68/Q(4) AND XLXI_70/XLXN_282)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	Blocked_inst/ps2)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(2) AND XLXI_70/XLXI_68/Q(3) AND 
	XLXI_70/XLXN_281 AND NOT XLXI_70/XLXN_282)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXI_68/Q(4))
	OR (NOT XLXI_70/XLXI_68/Q(4) AND NOT XLXI_70/XLXI_68/Q(1))
	OR (NOT XLXI_70/XLXI_68/Q(4) AND NOT XLXI_70/XLXI_68/Q(2))
	OR (NOT XLXI_70/XLXI_68/Q(4) AND NOT XLXI_70/XLXI_68/Q(3))
	OR (NOT XLXI_70/XLXI_68/Q(4) AND NOT XLXI_70/XLXN_281));

FDCPE_XLXI_70/XLXI_68/Q5: FDCPE port map (XLXI_70/XLXI_68/Q(5),XLXI_70/XLXI_68/Q_D(5),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(5) <= ((NOT XLXI_70/XLXI_68/Q(5) AND NOT XLXI_70/XLXN_281)
	OR (NOT XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXN_282)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	Blocked_inst/ps2)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXI_68/Q(2) AND 
	XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXN_281 AND NOT XLXI_70/XLXN_282)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXI_68/Q(5))
	OR (NOT XLXI_70/XLXI_68/Q(4) AND NOT XLXI_70/XLXI_68/Q(5))
	OR (NOT XLXI_70/XLXI_68/Q(1) AND NOT XLXI_70/XLXI_68/Q(5))
	OR (NOT XLXI_70/XLXI_68/Q(5) AND NOT XLXI_70/XLXI_68/Q(2))
	OR (NOT XLXI_70/XLXI_68/Q(5) AND NOT XLXI_70/XLXI_68/Q(3)));

FDCPE_XLXI_70/XLXI_68/Q6: FDCPE port map (XLXI_70/XLXI_68/Q(6),XLXI_70/XLXI_68/Q_D(6),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(6) <= ((NOT XLXI_70/XLXI_68/Q(5) AND NOT XLXI_70/XLXI_68/Q(6))
	OR (NOT XLXI_70/XLXI_68/Q(6) AND NOT XLXI_70/XLXN_281)
	OR (NOT XLXI_70/XLXI_68/Q(6) AND XLXI_70/XLXN_282)
	OR (Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Blocked_inst/ps0 AND NOT Blocked_inst/ps1 AND 
	Blocked_inst/ps2)
	OR (Loop_inst/PS0 AND NOT Loop_inst/PS1 AND NOT Loop_inst/PS2 AND 
	Loop_inst/PS3)
	OR (XLXI_70/XLXI_68/Q(0) AND XLXI_70/XLXI_68/Q(4) AND 
	XLXI_70/XLXI_68/Q(1) AND XLXI_70/XLXI_68/Q(5) AND XLXI_70/XLXI_68/Q(2) AND 
	XLXI_70/XLXI_68/Q(6) AND XLXI_70/XLXI_68/Q(3) AND XLXI_70/XLXN_281 AND 
	NOT XLXI_70/XLXN_282)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXI_68/Q(6))
	OR (NOT XLXI_70/XLXI_68/Q(4) AND NOT XLXI_70/XLXI_68/Q(6))
	OR (NOT XLXI_70/XLXI_68/Q(1) AND NOT XLXI_70/XLXI_68/Q(6))
	OR (NOT XLXI_70/XLXI_68/Q(2) AND NOT XLXI_70/XLXI_68/Q(6))
	OR (NOT XLXI_70/XLXI_68/Q(6) AND NOT XLXI_70/XLXI_68/Q(3)));

FDCPE_XLXI_70/XLXI_68/Q7: FDCPE port map (XLXI_70/XLXI_68/Q(7),XLXI_70/XLXI_68/Q_D(7),CLK,NOT CLR,'0');
XLXI_70/XLXI_68/Q_D(7) <= ((LED3_OBUF.EXP)
	OR (NOT XLXI_70/XLXI_68/Q(4) AND NOT XLXI_70/XLXI_68/Q(7))
	OR (NOT XLXI_70/XLXI_68/Q(5) AND NOT XLXI_70/XLXI_68/Q(7))
	OR (NOT XLXI_70/XLXI_68/Q(6) AND NOT XLXI_70/XLXI_68/Q(7))
	OR (NOT XLXI_70/XLXI_68/Q(7) AND NOT XLXI_70/XLXN_281)
	OR (NOT XLXI_70/XLXI_68/Q(7) AND XLXI_70/XLXN_282)
	OR (NOT XLXI_70/XLXI_68/Q(0) AND NOT XLXI_70/XLXI_68/Q(7))
	OR (NOT XLXI_70/XLXI_68/Q(1) AND NOT XLXI_70/XLXI_68/Q(7))
	OR (NOT XLXI_70/XLXI_68/Q(2) AND NOT XLXI_70/XLXI_68/Q(7))
	OR (NOT XLXI_70/XLXI_68/Q(3) AND NOT XLXI_70/XLXI_68/Q(7)));

FDCPE_XLXI_70/XLXN_281: FDCPE port map (XLXI_70/XLXN_281,Timer_In,CLK,NOT CLR,'0');

FDCPE_XLXI_70/XLXN_282: FDCPE port map (XLXI_70/XLXN_282,XLXI_70/XLXN_281,CLK,NOT CLR,'0');

FDCPE_looping_dir: FDCPE port map (looping_dir,looping_dir_D,CLK,NOT CLR,'0',update);
looping_dir_D <= (FL AND BL);

FDCPE_update: FDCPE port map (update,update_D,CLK,NOT CLR,'0');
update_D <= ((Obstacle_inst/ps0 AND NOT Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1)
	OR (NOT Obstacle_inst/ps0 AND Obstacle_inst/ps2 AND 
	NOT Obstacle_inst/ps1));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC9572XL-5-VQ44     29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 LED4                             23 KPR                           
  2 LED5                             24 TDO                           
  3 LED6                             25 GND                           
  4 GND                              26 VCC                           
  5 KPR                              27 KPR                           
  6 KPR                              28 KPR                           
  7 KPR                              29 KPR                           
  8 KPR                              30 KPR                           
  9 TDI                              31 KPR                           
 10 TMS                              32 Timer_In                      
 11 TCK                              33 CLR                           
 12 KPR                              34 RM1                           
 13 KPR                              35 VCC                           
 14 KPR                              36 RM0                           
 15 VCC                              37 LM1                           
 16 KPR                              38 LM0                           
 17 GND                              39 LED3                          
 18 KPR                              40 LED2                          
 19 FL                               41 LED1                          
 20 FR                               42 LED0                          
 21 BL                               43 KPR                           
 22 BR                               44 CLK                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
